📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity max_log_map is generic( SOFT_INFO_WIDTH : integer := 6; PRIOR_INFO_WIDTH: integer := 8; HD_DAT_WIDTH : integer := 2; BRANCH_MATRIC_WIDTH: integer := 9; STATE_MATRIC_WIDTH: integer := 12; LLR_INFO_WIDTH : integer := 12 ); port( clk_sys : in vl_logic; rst_b : in vl_logic; ys : in vl_logic_vector; yp : in vl_logic_vector; la : in vl_logic_vector; sop_source : in vl_logic; eop_source : in vl_logic; val_source : in vl_logic; packet_length : in vl_logic_vector(15 downto 0); d : out vl_logic_vector; le : out vl_logic_vector; l : out vl_logic_vector; sop_sink : out vl_logic; eop_sink : out vl_logic; val_sink : out vl_logic );end max_log_map;
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