_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 33 行

library verilog;
use verilog.vl_types.all;
entity stop_detect is
    generic(
        WIN_SIZE        : integer := 32;
        HD_DAT_WIDTH    : integer := 2;
        PRIOR_INFO_WIDTH: integer := 8;
        LLR_INFO_WIDTH  : integer := 12
    );
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        d               : in     vl_logic_vector;
        le              : in     vl_logic_vector;
        l               : in     vl_logic_vector;
        sop_sink        : in     vl_logic;
        eop_sink        : in     vl_logic;
        val_sink        : in     vl_logic;
        packet_length   : in     vl_logic_vector(15 downto 0);
        code_rate       : in     vl_logic_vector(2 downto 0);
        modulate_type   : in     vl_logic_vector(1 downto 0);
        max_iter_no     : in     vl_logic_vector(3 downto 0);
        real_iter_no    : out    vl_logic_vector(4 downto 0);
        iter_stop       : out    vl_logic;
        rd_int_ram      : out    vl_logic;
        dat_rd_int_ram  : in     vl_logic_vector(11 downto 0);
        adr_rd_int_ram  : out    vl_logic_vector(11 downto 0);
        rd_deint_ram    : out    vl_logic;
        dat_rd_deint_ram: in     vl_logic_vector(11 downto 0);
        adr_rd_deint_ram: out    vl_logic_vector(11 downto 0)
    );
end stop_detect;