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📄 _primary.vhd

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library verilog;use verilog.vl_types.all;entity ctc_decoder_datapath_top is    generic(        SOFT_INFO_WIDTH : integer := 6;        PRIOR_INFO_WIDTH: integer := 8;        LLR_INFO_WIDTH  : integer := 12;        OUT_FIFO_DEPTH_WIDTH: integer := 9    );    port(        clk_sys         : in     vl_logic;        rst_b           : in     vl_logic;        ys              : in     vl_logic_vector;        yp              : in     vl_logic_vector;        la              : in     vl_logic_vector;        sop_source      : in     vl_logic;        eop_source      : in     vl_logic;        val_source      : in     vl_logic;        le              : out    vl_logic_vector;        sop_sink        : out    vl_logic;        eop_sink        : out    vl_logic;        val_sink        : out    vl_logic;        iter_stop       : out    vl_logic;        packet_type     : in     vl_logic_vector(2 downto 0);        instance_num    : in     vl_logic_vector(1 downto 0);        packet_length   : in     vl_logic_vector(15 downto 0);        packet_frame_end_flag: in     vl_logic_vector(2 downto 0);        code_rate       : in     vl_logic_vector(2 downto 0);        modulate_type   : in     vl_logic_vector(1 downto 0);        burst_id        : in     vl_logic_vector(15 downto 0);        fec_id          : in     vl_logic_vector(7 downto 0);        max_iter_no     : in     vl_logic_vector(3 downto 0);        segId           : in     vl_logic_vector(3 downto 0);        fifo_usedword   : in     vl_logic_vector;        dat_wr_fifo     : out    vl_logic_vector(31 downto 0);        wr_fifo         : out    vl_logic;        int_deint_adr_gen_en: in     vl_logic;        rd_int_ram0     : in     vl_logic;        adr_rd_int_ram0 : in     vl_logic_vector(11 downto 0);        dat_rd_int_ram0 : out    vl_logic_vector(11 downto 0);        rd_deint_ram0   : in     vl_logic;        adr_rd_deint_ram0: in     vl_logic_vector(11 downto 0);        dat_rd_deint_ram0: out    vl_logic_vector(11 downto 0)    );end ctc_decoder_datapath_top;

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