_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 73 行

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_7 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha72_11      : in     vl_logic;
        alpha72_10      : in     vl_logic;
        alpha72_9       : in     vl_logic;
        alpha72_8       : in     vl_logic;
        alpha72_7       : in     vl_logic;
        alpha72_6       : in     vl_logic;
        alpha72_5       : in     vl_logic;
        alpha72_4       : in     vl_logic;
        alpha72_3       : in     vl_logic;
        alpha72_2       : in     vl_logic;
        alpha72_1       : in     vl_logic;
        alpha72_0       : in     vl_logic;
        alpha73_11      : in     vl_logic;
        alpha73_10      : in     vl_logic;
        alpha73_9       : in     vl_logic;
        alpha73_8       : in     vl_logic;
        alpha73_7       : in     vl_logic;
        alpha73_6       : in     vl_logic;
        alpha73_5       : in     vl_logic;
        alpha73_4       : in     vl_logic;
        alpha73_3       : in     vl_logic;
        alpha73_2       : in     vl_logic;
        alpha73_1       : in     vl_logic;
        alpha73_0       : in     vl_logic;
        alpha71_11      : in     vl_logic;
        alpha71_10      : in     vl_logic;
        alpha71_9       : in     vl_logic;
        alpha71_8       : in     vl_logic;
        alpha71_7       : in     vl_logic;
        alpha71_6       : in     vl_logic;
        alpha71_5       : in     vl_logic;
        alpha71_4       : in     vl_logic;
        alpha71_3       : in     vl_logic;
        alpha71_2       : in     vl_logic;
        alpha71_1       : in     vl_logic;
        alpha71_0       : in     vl_logic;
        alpha70_11      : in     vl_logic;
        alpha70_10      : in     vl_logic;
        alpha70_9       : in     vl_logic;
        alpha70_8       : in     vl_logic;
        alpha70_7       : in     vl_logic;
        alpha70_6       : in     vl_logic;
        alpha70_5       : in     vl_logic;
        alpha70_4       : in     vl_logic;
        alpha70_3       : in     vl_logic;
        alpha70_2       : in     vl_logic;
        alpha70_1       : in     vl_logic;
        alpha70_0       : in     vl_logic;
        alpha_t7_11     : out    vl_logic;
        alpha_t7_10     : out    vl_logic;
        alpha_t7_9      : out    vl_logic;
        alpha_t7_8      : out    vl_logic;
        alpha_t7_7      : out    vl_logic;
        alpha_t7_6      : out    vl_logic;
        alpha_t7_5      : out    vl_logic;
        alpha_t7_4      : out    vl_logic;
        alpha_t7_3      : out    vl_logic;
        alpha_t7_2      : out    vl_logic;
        alpha_t7_1      : out    vl_logic;
        alpha_t7_0      : out    vl_logic;
        G_139_combout   : in     vl_logic
    );
end mod_max4_a_7;