_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity alpha_cal is
    generic(
        SOFT_INFO_WIDTH : integer := 6;
        PRIOR_INFO_WIDTH: integer := 8;
        BRANCH_MATRIC_WIDTH: integer := 9;
        STATE_MATRIC_WIDTH: integer := 12
    );
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        ys              : in     vl_logic_vector;
        yp              : in     vl_logic_vector;
        la              : in     vl_logic_vector;
        alpha_source_val: in     vl_logic;
        clr_alpha       : in     vl_logic;
        alpha           : out    vl_logic_vector;
        alpha_sink_val  : out    vl_logic
    );
end alpha_cal;