_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity int_deint_adr_ram is
    port(
        address_a       : in     vl_logic_vector(11 downto 0);
        address_b       : in     vl_logic_vector(11 downto 0);
        clock           : in     vl_logic;
        data_a          : in     vl_logic_vector(11 downto 0);
        data_b          : in     vl_logic_vector(11 downto 0);
        wren_a          : in     vl_logic;
        wren_b          : in     vl_logic;
        q_a             : out    vl_logic_vector(11 downto 0);
        q_b             : out    vl_logic_vector(11 downto 0)
    );
end int_deint_adr_ram;