📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity pre_proc is generic( PROC_READY : integer := 1; PROC_HEAD : integer := 2; PROC_PACKET : integer := 4 ); port( clk_sys : in vl_logic; rst_b : in vl_logic; dat_rd : in vl_logic_vector(32 downto 0); empty : in vl_logic; rcser : in vl_logic; rd : out vl_logic; full_0 : in vl_logic; wr_0 : out vl_logic; eop_0 : out vl_logic; dat_wr_0 : out vl_logic_vector(31 downto 0); full_1 : in vl_logic; wr_1 : out vl_logic; eop_1 : out vl_logic; dat_wr_1 : out vl_logic_vector(31 downto 0); full_2 : in vl_logic; wr_2 : out vl_logic; eop_2 : out vl_logic; dat_wr_2 : out vl_logic_vector(31 downto 0); excep_pre_proc : out vl_logic_vector(1 downto 0); rx_packet_counter: out vl_logic_vector(31 downto 0) );end pre_proc;
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