_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity int_deint_adr_gen_mul is
    port(
        aclr            : in     vl_logic;
        clock           : in     vl_logic;
        dataa           : in     vl_logic_vector(11 downto 0);
        datab           : in     vl_logic_vector(5 downto 0);
        result          : out    vl_logic_vector(17 downto 0)
    );
end int_deint_adr_gen_mul;