_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 29 行

library verilog;
use verilog.vl_types.all;
entity ctc_rx_arb is
    generic(
        CTC_FIFO_THRESHOLD: integer := 340;
        IDLE            : integer := 1;
        SEARCH          : integer := 2;
        ST_WAIT         : integer := 4
    );
    port(
        core1_req       : in     vl_logic;
        core1_gnt       : out    vl_logic;
        core2_req       : in     vl_logic;
        core2_gnt       : out    vl_logic;
        core3_req       : in     vl_logic;
        core3_gnt       : out    vl_logic;
        p_len           : in     vl_logic_vector(15 downto 0);
        empty           : in     vl_logic;
        wr1_over        : in     vl_logic;
        wr2_over        : in     vl_logic;
        wr3_over        : in     vl_logic;
        ctc_fifo1_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo2_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo3_usedw : in     vl_logic_vector(8 downto 0);
        sys_clk         : in     vl_logic;
        reset_b         : in     vl_logic
    );
end ctc_rx_arb;