_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity int_deint_adr_gen is
    generic(
        READY           : integer := 1;
        RUN             : integer := 2
    );
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        int_deint_adr_gen_en: in     vl_logic;
        packet_length   : in     vl_logic_vector(15 downto 0);
        rd_int_ram0     : in     vl_logic;
        adr_rd_int_ram0 : in     vl_logic_vector(11 downto 0);
        dat_rd_int_ram0 : out    vl_logic_vector(11 downto 0);
        rd_int_ram1     : in     vl_logic;
        adr_rd_int_ram1 : in     vl_logic_vector(11 downto 0);
        dat_rd_int_ram1 : out    vl_logic_vector(11 downto 0);
        rd_deint_ram0   : in     vl_logic;
        adr_rd_deint_ram0: in     vl_logic_vector(11 downto 0);
        dat_rd_deint_ram0: out    vl_logic_vector(11 downto 0);
        rd_deint_ram1   : in     vl_logic;
        adr_rd_deint_ram1: in     vl_logic_vector(11 downto 0);
        dat_rd_deint_ram1: out    vl_logic_vector(11 downto 0)
    );
end int_deint_adr_gen;