_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity lp_tx is
    generic(
        DEVICE          : string  := "Stratix II"
    );
    port(
        clk             : in     vl_logic;
        clk270          : in     vl_logic;
        clk4            : in     vl_logic;
        rst_n           : in     vl_logic;
        tvere           : in     vl_logic;
        tx_wr           : in     vl_logic;
        tx_wdata        : in     vl_logic_vector(32 downto 0);
        tx_wrused       : out    vl_logic_vector(3 downto 0);
        tx_wrfull       : out    vl_logic;
        clk_out         : out    vl_logic;
        data_out        : out    vl_logic_vector(3 downto 0);
        acki            : in     vl_logic;
        bcmpo_n         : out    vl_logic
    );
end lp_tx;