_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity stratixii_lvds_rx_bitslip is
    generic(
        channel_width   : integer := 10;
        bitslip_rollover: integer := 12
    );
    port(
        clk0            : in     vl_logic;
        bslipcntl       : in     vl_logic;
        bsliprst        : in     vl_logic;
        datain          : in     vl_logic;
        bslipmax        : out    vl_logic;
        dataout         : out    vl_logic
    );
end stratixii_lvds_rx_bitslip;