_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 73 行

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_3 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha32_11      : in     vl_logic;
        alpha32_10      : in     vl_logic;
        alpha32_9       : in     vl_logic;
        alpha32_8       : in     vl_logic;
        alpha32_7       : in     vl_logic;
        alpha32_6       : in     vl_logic;
        alpha32_5       : in     vl_logic;
        alpha32_4       : in     vl_logic;
        alpha32_3       : in     vl_logic;
        alpha32_2       : in     vl_logic;
        alpha32_1       : in     vl_logic;
        alpha32_0       : in     vl_logic;
        alpha33_11      : in     vl_logic;
        alpha33_10      : in     vl_logic;
        alpha33_9       : in     vl_logic;
        alpha33_8       : in     vl_logic;
        alpha33_7       : in     vl_logic;
        alpha33_6       : in     vl_logic;
        alpha33_5       : in     vl_logic;
        alpha33_4       : in     vl_logic;
        alpha33_3       : in     vl_logic;
        alpha33_2       : in     vl_logic;
        alpha33_1       : in     vl_logic;
        alpha33_0       : in     vl_logic;
        alpha31_11      : in     vl_logic;
        alpha31_10      : in     vl_logic;
        alpha31_9       : in     vl_logic;
        alpha31_8       : in     vl_logic;
        alpha31_7       : in     vl_logic;
        alpha31_6       : in     vl_logic;
        alpha31_5       : in     vl_logic;
        alpha31_4       : in     vl_logic;
        alpha31_3       : in     vl_logic;
        alpha31_2       : in     vl_logic;
        alpha31_1       : in     vl_logic;
        alpha31_0       : in     vl_logic;
        alpha30_11      : in     vl_logic;
        alpha30_10      : in     vl_logic;
        alpha30_9       : in     vl_logic;
        alpha30_8       : in     vl_logic;
        alpha30_7       : in     vl_logic;
        alpha30_6       : in     vl_logic;
        alpha30_5       : in     vl_logic;
        alpha30_4       : in     vl_logic;
        alpha30_3       : in     vl_logic;
        alpha30_2       : in     vl_logic;
        alpha30_1       : in     vl_logic;
        alpha30_0       : in     vl_logic;
        alpha_t3_11     : out    vl_logic;
        alpha_t3_10     : out    vl_logic;
        alpha_t3_9      : out    vl_logic;
        alpha_t3_8      : out    vl_logic;
        alpha_t3_7      : out    vl_logic;
        alpha_t3_6      : out    vl_logic;
        alpha_t3_5      : out    vl_logic;
        alpha_t3_4      : out    vl_logic;
        alpha_t3_3      : out    vl_logic;
        alpha_t3_2      : out    vl_logic;
        alpha_t3_1      : out    vl_logic;
        alpha_t3_0      : out    vl_logic;
        G_91_combout    : in     vl_logic
    );
end mod_max4_a_3;