_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 35 行

library verilog;
use verilog.vl_types.all;
entity fec_mux is
    generic(
        OUT_ARBITRATE   : integer := 1;
        GET_HEAD        : integer := 2;
        PROC_HEAD       : integer := 4;
        PROC_PACKET     : integer := 8;
        SEL_TBCC        : integer := 1;
        SEL_CTC         : integer := 2;
        SEL_LDPC        : integer := 4
    );
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        empty_0         : in     vl_logic;
        rd_0            : out    vl_logic;
        eop_rd_0        : in     vl_logic;
        dat_rd_0        : in     vl_logic_vector(31 downto 0);
        empty_1         : in     vl_logic;
        rd_1            : out    vl_logic;
        eop_rd_1        : in     vl_logic;
        dat_rd_1        : in     vl_logic_vector(31 downto 0);
        empty_2         : in     vl_logic;
        rd_2            : out    vl_logic;
        eop_rd_2        : in     vl_logic;
        dat_rd_2        : in     vl_logic_vector(31 downto 0);
        tvere           : out    vl_logic;
        tx_wr           : out    vl_logic;
        tx_wdata        : out    vl_logic_vector(32 downto 0);
        tx_wrfull       : in     vl_logic;
        tx_packet_counter: out    vl_logic_vector(31 downto 0)
    );
end fec_mux;