_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity lp_rx is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        datain          : in     vl_logic_vector(3 downto 0);
        inclock         : in     vl_logic;
        inclock_en      : in     vl_logic;
        acko            : out    vl_logic;
        bcmpi_n         : in     vl_logic;
        rvere           : in     vl_logic;
        rcser           : out    vl_logic;
        clr_rcser       : in     vl_logic;
        rdreq           : in     vl_logic;
        empty           : out    vl_logic;
        rdata           : out    vl_logic_vector(32 downto 0)
    );
end lp_rx;