_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity tbcc_decoder_bypass is
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        empty_pre_vit_fifo: in     vl_logic;
        rd_pre_vit_fifo : out    vl_logic;
        eop_rd_pre_vit_fifo: in     vl_logic;
        dat_rd_pre_vit_fifo: in     vl_logic_vector(31 downto 0);
        full_post_vit_fifo: in     vl_logic;
        wr_post_vit_fifo: out    vl_logic;
        eop_wr_post_vit_fifo: out    vl_logic;
        dat_wr_post_vit_fifo: out    vl_logic_vector(31 downto 0);
        wrusedword_post_vit_fifo: in     vl_logic_vector(7 downto 0)
    );
end tbcc_decoder_bypass;