_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity int_deint_adr_gen_para_rom is
    port(
        address         : in     vl_logic_vector(4 downto 0);
        clock           : in     vl_logic;
        q               : out    vl_logic_vector(35 downto 0)
    );
end int_deint_adr_gen_para_rom;