📄 _primary.vhd
字号:
library verilog;use verilog.vl_types.all;entity l_le_hd_cal is generic( SOFT_INFO_WIDTH : integer := 6; PRIOR_INFO_WIDTH: integer := 8; BRANCH_MATRIC_WIDTH: integer := 9; STATE_MATRIC_WIDTH: integer := 12; LLR_INFO_WIDTH : integer := 12; LC_WIDTH : integer := 8; LE_CAL_WIDTH : integer := 15 ); port( clk_sys : in vl_logic; rst_b : in vl_logic; alpha : in vl_logic_vector; beta : in vl_logic_vector; gamma : in vl_logic_vector; ys : in vl_logic_vector; la : in vl_logic_vector; l_source_val : in vl_logic; clr_l : in vl_logic; d : out vl_logic_vector(1 downto 0); le : out vl_logic_vector; l : out vl_logic_vector; l_sink_val : out vl_logic );end l_le_hd_cal;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -