_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 28 行

library verilog;
use verilog.vl_types.all;
entity block_cir_buf is
    generic(
        SOFT_INFO_WIDTH : integer := 6;
        PRIOR_INFO_WIDTH: integer := 8;
        WIN_SIZE        : integer := 32;
        CIR_BUF_ADR_SIZE: integer := 6
    );
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        ys              : in     vl_logic_vector;
        yp              : in     vl_logic_vector;
        la              : in     vl_logic_vector;
        sop_source      : in     vl_logic;
        eop_source      : in     vl_logic;
        val_source      : in     vl_logic;
        clr_cir_buf     : in     vl_logic;
        rd_cir_buf_cell0: in     vl_logic;
        rd_cir_buf_cell1: in     vl_logic;
        rd_cir_buf_cell2: in     vl_logic;
        output_dat0     : out    vl_logic_vector;
        output_dat1     : out    vl_logic_vector;
        output_dat2     : out    vl_logic_vector
    );
end block_cir_buf;