📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity alpha_buf is generic( WIN_SIZE : integer := 32; STATE_MATRIC_WIDTH: integer := 12; ALPHA_RAM_ADR_WIDTH: integer := 7 ); port( clk_sys : in vl_logic; rst_b : in vl_logic; alpha : in vl_logic_vector; alpha_source_val: in vl_logic; clr_alpha_buf : in vl_logic; alpha_buf_out : out vl_logic_vector; rd_alpha_buf : in vl_logic );end alpha_buf;
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