_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity fec_decoder_top is
    port(
        clk_4chip       : in     vl_logic;
        rst_b           : in     vl_logic;
        datain          : in     vl_logic_vector(3 downto 0);
        inclock         : in     vl_logic;
        acko            : out    vl_logic;
        bcmpi_n         : in     vl_logic;
        clk_out         : out    vl_logic;
        data_out        : out    vl_logic_vector(3 downto 0);
        acki            : in     vl_logic;
        bcmpo_n         : out    vl_logic
    );
end fec_decoder_top;