_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity ctc_rx_fsm is
    generic(
        IDLE            : integer := 1;
        HEAD            : integer := 2;
        WT1             : integer := 4;
        WT2             : integer := 8;
        LEN             : integer := 16;
        WAIT1           : integer := 32;
        WAIT2           : integer := 64;
        READ1           : integer := 128;
        W_SRG1          : integer := 256;
        READ2           : integer := 512;
        WR_SRG2         : integer := 1024;
        READ3           : integer := 2048;
        WR_SRG3         : integer := 4096
    );
    port(
        empty           : in     vl_logic;
        usedw           : in     vl_logic_vector(12 downto 0);
        eop_rd          : in     vl_logic;
        dat_rd          : in     vl_logic_vector(31 downto 0);
        rd              : out    vl_logic;
        core1_req       : in     vl_logic;
        core1_gnt       : out    vl_logic;
        wr1_over        : out    vl_logic;
        rx2ctrl1_length : out    vl_logic_vector(15 downto 0);
        rx2ctrl1_type   : out    vl_logic_vector(2 downto 0);
        rx2ctrl1_inst   : out    vl_logic_vector(1 downto 0);
        rx2ctrl1_code_rate: out    vl_logic_vector(2 downto 0);
        rx2ctrl1_modu_type: out    vl_logic_vector(1 downto 0);
        rx2ctrl1_bnum   : out    vl_logic_vector(15 downto 0);
        rx2ctrl1_fnum   : out    vl_logic_vector(7 downto 0);
        rx2ctrl1_miter  : out    vl_logic_vector(3 downto 0);
        rx2ctrl1_segId  : out    vl_logic_vector(3 downto 0);
        rx2ctrl1_frame_end_flag: out    vl_logic_vector(2 downto 0);
        core2_req       : in     vl_logic;
        core2_gnt       : out    vl_logic;
        wr2_over        : out    vl_logic;
        rx2ctrl2_length : out    vl_logic_vector(15 downto 0);
        rx2ctrl2_type   : out    vl_logic_vector(2 downto 0);
        rx2ctrl2_inst   : out    vl_logic_vector(1 downto 0);
        rx2ctrl2_code_rate: out    vl_logic_vector(2 downto 0);
        rx2ctrl2_modu_type: out    vl_logic_vector(1 downto 0);
        rx2ctrl2_bnum   : out    vl_logic_vector(15 downto 0);
        rx2ctrl2_fnum   : out    vl_logic_vector(7 downto 0);
        rx2ctrl2_miter  : out    vl_logic_vector(3 downto 0);
        rx2ctrl2_segId  : out    vl_logic_vector(3 downto 0);
        rx2ctrl2_frame_end_flag: out    vl_logic_vector(2 downto 0);
        core3_req       : in     vl_logic;
        core3_gnt       : out    vl_logic;
        wr3_over        : out    vl_logic;
        rx2ctrl3_length : out    vl_logic_vector(15 downto 0);
        rx2ctrl3_type   : out    vl_logic_vector(2 downto 0);
        rx2ctrl3_inst   : out    vl_logic_vector(1 downto 0);
        rx2ctrl3_code_rate: out    vl_logic_vector(2 downto 0);
        rx2ctrl3_modu_type: out    vl_logic_vector(1 downto 0);
        rx2ctrl3_bnum   : out    vl_logic_vector(15 downto 0);
        rx2ctrl3_fnum   : out    vl_logic_vector(7 downto 0);
        rx2ctrl3_miter  : out    vl_logic_vector(3 downto 0);
        rx2ctrl3_segId  : out    vl_logic_vector(3 downto 0);
        rx2ctrl3_frame_end_flag: out    vl_logic_vector(2 downto 0);
        dpram11_wrdat   : out    vl_logic_vector(23 downto 0);
        dpram11_wr      : out    vl_logic;
        dpram11_wradr   : out    vl_logic_vector(10 downto 0);
        dpram12_wrdat   : out    vl_logic_vector(47 downto 0);
        dpram12_wr      : out    vl_logic;
        dpram12_wradr   : out    vl_logic_vector(10 downto 0);
        dpram21_wrdat   : out    vl_logic_vector(23 downto 0);
        dpram21_wr      : out    vl_logic;
        dpram21_wradr   : out    vl_logic_vector(10 downto 0);
        dpram22_wrdat   : out    vl_logic_vector(47 downto 0);
        dpram22_wr      : out    vl_logic;
        dpram22_wradr   : out    vl_logic_vector(10 downto 0);
        dpram31_wrdat   : out    vl_logic_vector(23 downto 0);
        dpram31_wr      : out    vl_logic;
        dpram31_wradr   : out    vl_logic_vector(10 downto 0);
        dpram32_wrdat   : out    vl_logic_vector(47 downto 0);
        dpram32_wr      : out    vl_logic;
        dpram32_wradr   : out    vl_logic_vector(10 downto 0);
        ctc_fifo1_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo2_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo3_usedw : in     vl_logic_vector(8 downto 0);
        sys_clk         : in     vl_logic;
        reset_b         : in     vl_logic;
        rx_counter1_nc  : out    vl_logic_vector(15 downto 0);
        rx_counter2_nc  : out    vl_logic_vector(15 downto 0);
        rx_counter3_nc  : out    vl_logic_vector(15 downto 0)
    );
end ctc_rx_fsm;