_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_5 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha52_11      : in     vl_logic;
        alpha52_10      : in     vl_logic;
        alpha52_9       : in     vl_logic;
        alpha52_8       : in     vl_logic;
        alpha52_7       : in     vl_logic;
        alpha52_6       : in     vl_logic;
        alpha52_5       : in     vl_logic;
        alpha52_4       : in     vl_logic;
        alpha52_3       : in     vl_logic;
        alpha52_2       : in     vl_logic;
        alpha52_1       : in     vl_logic;
        alpha52_0       : in     vl_logic;
        alpha53_11      : in     vl_logic;
        alpha53_10      : in     vl_logic;
        alpha53_9       : in     vl_logic;
        alpha53_8       : in     vl_logic;
        alpha53_7       : in     vl_logic;
        alpha53_6       : in     vl_logic;
        alpha53_5       : in     vl_logic;
        alpha53_4       : in     vl_logic;
        alpha53_3       : in     vl_logic;
        alpha53_2       : in     vl_logic;
        alpha53_1       : in     vl_logic;
        alpha53_0       : in     vl_logic;
        alpha51_11      : in     vl_logic;
        alpha51_10      : in     vl_logic;
        alpha51_9       : in     vl_logic;
        alpha51_8       : in     vl_logic;
        alpha51_7       : in     vl_logic;
        alpha51_6       : in     vl_logic;
        alpha51_5       : in     vl_logic;
        alpha51_4       : in     vl_logic;
        alpha51_3       : in     vl_logic;
        alpha51_2       : in     vl_logic;
        alpha51_1       : in     vl_logic;
        alpha51_0       : in     vl_logic;
        alpha50_11      : in     vl_logic;
        alpha50_10      : in     vl_logic;
        alpha50_9       : in     vl_logic;
        alpha50_8       : in     vl_logic;
        alpha50_7       : in     vl_logic;
        alpha50_6       : in     vl_logic;
        alpha50_5       : in     vl_logic;
        alpha50_4       : in     vl_logic;
        alpha50_3       : in     vl_logic;
        alpha50_2       : in     vl_logic;
        alpha50_1       : in     vl_logic;
        alpha50_0       : in     vl_logic;
        alpha_t5_11     : out    vl_logic;
        alpha_t5_10     : out    vl_logic;
        alpha_t5_9      : out    vl_logic;
        alpha_t5_8      : out    vl_logic;
        alpha_t5_7      : out    vl_logic;
        alpha_t5_6      : out    vl_logic;
        alpha_t5_5      : out    vl_logic;
        alpha_t5_4      : out    vl_logic;
        alpha_t5_3      : out    vl_logic;
        alpha_t5_2      : out    vl_logic;
        alpha_t5_1      : out    vl_logic;
        alpha_t5_0      : out    vl_logic;
        G_115_combout   : in     vl_logic
    );
end mod_max4_a_5;