_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity mod_max4_a is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha02_11      : in     vl_logic;
        alpha02_10      : in     vl_logic;
        alpha02_9       : in     vl_logic;
        alpha02_8       : in     vl_logic;
        alpha02_7       : in     vl_logic;
        alpha02_6       : in     vl_logic;
        alpha02_5       : in     vl_logic;
        alpha02_4       : in     vl_logic;
        alpha02_3       : in     vl_logic;
        alpha02_2       : in     vl_logic;
        alpha02_1       : in     vl_logic;
        alpha02_0       : in     vl_logic;
        alpha03_11      : in     vl_logic;
        alpha03_10      : in     vl_logic;
        alpha03_9       : in     vl_logic;
        alpha03_8       : in     vl_logic;
        alpha03_7       : in     vl_logic;
        alpha03_6       : in     vl_logic;
        alpha03_5       : in     vl_logic;
        alpha03_4       : in     vl_logic;
        alpha03_3       : in     vl_logic;
        alpha03_2       : in     vl_logic;
        alpha03_1       : in     vl_logic;
        alpha03_0       : in     vl_logic;
        alpha01_11      : in     vl_logic;
        alpha01_10      : in     vl_logic;
        alpha01_9       : in     vl_logic;
        alpha01_8       : in     vl_logic;
        alpha01_7       : in     vl_logic;
        alpha01_6       : in     vl_logic;
        alpha01_5       : in     vl_logic;
        alpha01_4       : in     vl_logic;
        alpha01_3       : in     vl_logic;
        alpha01_2       : in     vl_logic;
        alpha01_1       : in     vl_logic;
        alpha01_0       : in     vl_logic;
        alpha00_11      : in     vl_logic;
        alpha00_10      : in     vl_logic;
        alpha00_9       : in     vl_logic;
        alpha00_8       : in     vl_logic;
        alpha00_7       : in     vl_logic;
        alpha00_6       : in     vl_logic;
        alpha00_5       : in     vl_logic;
        alpha00_4       : in     vl_logic;
        alpha00_3       : in     vl_logic;
        alpha00_2       : in     vl_logic;
        alpha00_1       : in     vl_logic;
        alpha00_0       : in     vl_logic;
        alpha_t0_11     : out    vl_logic;
        alpha_t0_10     : out    vl_logic;
        alpha_t0_9      : out    vl_logic;
        alpha_t0_8      : out    vl_logic;
        alpha_t0_7      : out    vl_logic;
        alpha_t0_6      : out    vl_logic;
        alpha_t0_5      : out    vl_logic;
        alpha_t0_4      : out    vl_logic;
        alpha_t0_3      : out    vl_logic;
        alpha_t0_2      : out    vl_logic;
        alpha_t0_1      : out    vl_logic;
        alpha_t0_0      : out    vl_logic;
        G_55_combout    : in     vl_logic
    );
end mod_max4_a;