_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity true_dpram is
    port(
        data            : in     vl_logic_vector(16 downto 0);
        rd_aclr         : in     vl_logic;
        rdaddress       : in     vl_logic_vector(6 downto 0);
        rdclock         : in     vl_logic;
        rden            : in     vl_logic;
        wraddress       : in     vl_logic_vector(7 downto 0);
        wrclock         : in     vl_logic;
        wren            : in     vl_logic;
        q               : out    vl_logic_vector(33 downto 0)
    );
end true_dpram;