_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity decoder_para_fifo is
    port(
        data            : in     vl_logic_vector(55 downto 0);
        wrreq           : in     vl_logic;
        rdreq           : in     vl_logic;
        clock           : in     vl_logic;
        aclr            : in     vl_logic;
        q               : out    vl_logic_vector(55 downto 0);
        full            : out    vl_logic;
        empty           : out    vl_logic;
        usedw           : out    vl_logic_vector(6 downto 0)
    );
end decoder_para_fifo;