_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 73 行

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_1 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha12_11      : in     vl_logic;
        alpha12_10      : in     vl_logic;
        alpha12_9       : in     vl_logic;
        alpha12_8       : in     vl_logic;
        alpha12_7       : in     vl_logic;
        alpha12_6       : in     vl_logic;
        alpha12_5       : in     vl_logic;
        alpha12_4       : in     vl_logic;
        alpha12_3       : in     vl_logic;
        alpha12_2       : in     vl_logic;
        alpha12_1       : in     vl_logic;
        alpha12_0       : in     vl_logic;
        alpha13_11      : in     vl_logic;
        alpha13_10      : in     vl_logic;
        alpha13_9       : in     vl_logic;
        alpha13_8       : in     vl_logic;
        alpha13_7       : in     vl_logic;
        alpha13_6       : in     vl_logic;
        alpha13_5       : in     vl_logic;
        alpha13_4       : in     vl_logic;
        alpha13_3       : in     vl_logic;
        alpha13_2       : in     vl_logic;
        alpha13_1       : in     vl_logic;
        alpha13_0       : in     vl_logic;
        alpha11_11      : in     vl_logic;
        alpha11_10      : in     vl_logic;
        alpha11_9       : in     vl_logic;
        alpha11_8       : in     vl_logic;
        alpha11_7       : in     vl_logic;
        alpha11_6       : in     vl_logic;
        alpha11_5       : in     vl_logic;
        alpha11_4       : in     vl_logic;
        alpha11_3       : in     vl_logic;
        alpha11_2       : in     vl_logic;
        alpha11_1       : in     vl_logic;
        alpha11_0       : in     vl_logic;
        alpha10_11      : in     vl_logic;
        alpha10_10      : in     vl_logic;
        alpha10_9       : in     vl_logic;
        alpha10_8       : in     vl_logic;
        alpha10_7       : in     vl_logic;
        alpha10_6       : in     vl_logic;
        alpha10_5       : in     vl_logic;
        alpha10_4       : in     vl_logic;
        alpha10_3       : in     vl_logic;
        alpha10_2       : in     vl_logic;
        alpha10_1       : in     vl_logic;
        alpha10_0       : in     vl_logic;
        alpha_t1_11     : out    vl_logic;
        alpha_t1_10     : out    vl_logic;
        alpha_t1_9      : out    vl_logic;
        alpha_t1_8      : out    vl_logic;
        alpha_t1_7      : out    vl_logic;
        alpha_t1_6      : out    vl_logic;
        alpha_t1_5      : out    vl_logic;
        alpha_t1_4      : out    vl_logic;
        alpha_t1_3      : out    vl_logic;
        alpha_t1_2      : out    vl_logic;
        alpha_t1_1      : out    vl_logic;
        alpha_t1_0      : out    vl_logic;
        G_67_combout    : in     vl_logic
    );
end mod_max4_a_1;