📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity post_ctc_fifo is port( clk_wr_fifo : in vl_logic; clk_rd_fifo : in vl_logic; rst_b : in vl_logic; full : out vl_logic; wr : in vl_logic; eop_wr : in vl_logic; dat_wr : in vl_logic_vector(31 downto 0); wrusedw : out vl_logic_vector(8 downto 0); empty : out vl_logic; rd : in vl_logic; eop_rd : out vl_logic; dat_rd : out vl_logic_vector(31 downto 0) );end post_ctc_fifo;
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