_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 73 行

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_2 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha22_11      : in     vl_logic;
        alpha22_10      : in     vl_logic;
        alpha22_9       : in     vl_logic;
        alpha22_8       : in     vl_logic;
        alpha22_7       : in     vl_logic;
        alpha22_6       : in     vl_logic;
        alpha22_5       : in     vl_logic;
        alpha22_4       : in     vl_logic;
        alpha22_3       : in     vl_logic;
        alpha22_2       : in     vl_logic;
        alpha22_1       : in     vl_logic;
        alpha22_0       : in     vl_logic;
        alpha23_11      : in     vl_logic;
        alpha23_10      : in     vl_logic;
        alpha23_9       : in     vl_logic;
        alpha23_8       : in     vl_logic;
        alpha23_7       : in     vl_logic;
        alpha23_6       : in     vl_logic;
        alpha23_5       : in     vl_logic;
        alpha23_4       : in     vl_logic;
        alpha23_3       : in     vl_logic;
        alpha23_2       : in     vl_logic;
        alpha23_1       : in     vl_logic;
        alpha23_0       : in     vl_logic;
        alpha21_11      : in     vl_logic;
        alpha21_10      : in     vl_logic;
        alpha21_9       : in     vl_logic;
        alpha21_8       : in     vl_logic;
        alpha21_7       : in     vl_logic;
        alpha21_6       : in     vl_logic;
        alpha21_5       : in     vl_logic;
        alpha21_4       : in     vl_logic;
        alpha21_3       : in     vl_logic;
        alpha21_2       : in     vl_logic;
        alpha21_1       : in     vl_logic;
        alpha21_0       : in     vl_logic;
        alpha20_11      : in     vl_logic;
        alpha20_10      : in     vl_logic;
        alpha20_9       : in     vl_logic;
        alpha20_8       : in     vl_logic;
        alpha20_7       : in     vl_logic;
        alpha20_6       : in     vl_logic;
        alpha20_5       : in     vl_logic;
        alpha20_4       : in     vl_logic;
        alpha20_3       : in     vl_logic;
        alpha20_2       : in     vl_logic;
        alpha20_1       : in     vl_logic;
        alpha20_0       : in     vl_logic;
        alpha_t2_11     : out    vl_logic;
        alpha_t2_10     : out    vl_logic;
        alpha_t2_9      : out    vl_logic;
        alpha_t2_8      : out    vl_logic;
        alpha_t2_7      : out    vl_logic;
        alpha_t2_6      : out    vl_logic;
        alpha_t2_5      : out    vl_logic;
        alpha_t2_4      : out    vl_logic;
        alpha_t2_3      : out    vl_logic;
        alpha_t2_2      : out    vl_logic;
        alpha_t2_1      : out    vl_logic;
        alpha_t2_0      : out    vl_logic;
        G_79_combout    : in     vl_logic
    );
end mod_max4_a_2;