clk_div.vhd

来自「用VHDL语言实现QPSK调制功能和解调功能,」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clk_div is
	port (clk: in std_logic;
	      clkdiv: out std_logic
		   );
end clk_div;

architecture rel of clk_div is
     signal count: std_logic_vector(7 downto 0);
     signal clk_temp: std_logic;
 begin
	process(clk)
	begin
		if (clk'event and clk='0') then
		      if (count="1000011") then 
			      count<= (others =>'0');
                              clk_temp <= not clk_temp;
			  else 
                              count <= count+1;
			end if;
		end if;
end process;
clkdiv <= clk_temp;
end rel;