qpsktiao.map.qmsg

用VHDL语言实现QPSK调制功能和解调功能,

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 09 10:38:40 2008 " "Info: Processing started: Fri May 09 10:38:40 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qpsktiao -c qpsktiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qpsktiao -c qpsktiao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qpsktiao.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file qpsktiao.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 qpsktiao " "Info: Found entity 1: qpsktiao" {  } { { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qpsktiao " "Info: Elaborating entity \"qpsktiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "q counter8 inst1 " "Warning: Port \"q\" of type counter8 and instance \"inst1\" is missing source signal" {  } { { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 280 456 576 408 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tiaopin.vhd 2 1 " "Warning: Using design file tiaopin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tiaopin-rtl " "Info: Found design unit 1: tiaopin-rtl" {  } { { "tiaopin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/tiaopin.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tiaopin " "Info: Found entity 1: tiaopin" {  } { { "tiaopin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/tiaopin.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tiaopin tiaopin:inst5 " "Info: Elaborating entity \"tiaopin\" for hierarchy \"tiaopin:inst5\"" {  } { { "qpsktiao.bdf" "inst5" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 104 264 360 200 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clk_div.vhd 2 1 " "Warning: Using design file clk_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_div-rel " "Info: Found design unit 1: clk_div-rel" {  } { { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:inst " "Info: Elaborating entity \"clk_div\" for hierarchy \"clk_div:inst\"" {  } { { "qpsktiao.bdf" "inst" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { -24 256 352 72 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fenpin.vhd 2 1 " "Warning: Using design file fenpin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-rtl " "Info: Found design unit 1: fenpin-rtl" {  } { { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:inst2 " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:inst2\"" {  } { { "qpsktiao.bdf" "inst2" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 48 -120 -8 144 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter8.vhd 2 1 " "Warning: Using design file counter8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter8-rel " "Info: Found design unit 1: counter8-rel" {  } { { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter8 " "Info: Found entity 1: counter8" {  } { { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter8 counter8:inst1 " "Info: Elaborating entity \"counter8\" for hierarchy \"counter8:inst1\"" {  } { { "qpsktiao.bdf" "inst1" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 280 456 576 408 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "select4_1.vhd 2 1 " "Warning: Using design file select4_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 select4_1-rel " "Info: Found design unit 1: select4_1-rel" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 select4_1 " "Info: Found entity 1: select4_1" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "select4_1 select4_1:inst3 " "Info: Elaborating entity \"select4_1\" for hierarchy \"select4_1:inst3\"" {  } { { "qpsktiao.bdf" "inst3" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 312 192 320 408 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "seri_2.vhd 2 1 " "Warning: Using design file seri_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seri_2-rel " "Info: Found design unit 1: seri_2-rel" {  } { { "seri_2.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/seri_2.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seri_2 " "Info: Found entity 1: seri_2" {  } { { "seri_2.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/seri_2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seri_2 seri_2:inst4 " "Info: Elaborating entity \"seri_2\" for hierarchy \"seri_2:inst4\"" {  } { { "qpsktiao.bdf" "inst4" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 328 24 120 424 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "select4_1:inst3\|q\[7\] data_in GND " "Warning: Reduced register \"select4_1:inst3\|q\[7\]\" with stuck data_in port to stuck value GND" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "select4_1:inst3\|q\[4\] select4_1:inst3\|q\[0\] " "Info: Duplicate register \"select4_1:inst3\|q\[4\]\" merged to single register \"select4_1:inst3\|q\[0\]\"" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "select4_1:inst3\|q\[3\] select4_1:inst3\|q\[0\] " "Info: Duplicate register \"select4_1:inst3\|q\[3\]\" merged to single register \"select4_1:inst3\|q\[0\]\"" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "select4_1:inst3\|q\[2\] select4_1:inst3\|q\[0\] " "Info: Duplicate register \"select4_1:inst3\|q\[2\]\" merged to single register \"select4_1:inst3\|q\[0\]\"" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "select4_1:inst3\|q\[1\] select4_1:inst3\|q\[0\] " "Info: Duplicate register \"select4_1:inst3\|q\[1\]\" merged to single register \"select4_1:inst3\|q\[0\]\"" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fenpin:inst2\|count\[0\] tiaopin:inst5\|m\[0\] " "Info: Duplicate register \"fenpin:inst2\|count\[0\]\" merged to single register \"tiaopin:inst5\|m\[0\]\"" {  } { { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 22 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fenpin:inst2\|count\[1\] tiaopin:inst5\|m\[1\] " "Info: Duplicate register \"fenpin:inst2\|count\[1\]\" merged to single register \"tiaopin:inst5\|m\[1\]\"" {  } { { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 22 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "qm\[7\] GND " "Warning: Pin \"qm\[7\]\" stuck at GND" {  } { { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 472 360 536 488 "qm\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "21 " "Info: Implemented 21 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "48 " "Info: Implemented 48 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:38:45 2008 " "Info: Processing ended: Fri May 09 10:38:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}