fenpin.vhd

来自「用VHDL语言实现QPSK调制功能和解调功能,」· VHDL 代码 · 共 35 行

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 


ENTITY fenpin is
PORT(clk : IN STD_LOGIC;
                           --start : in std_logic; 
                           --clk_div2 : OUT STD_LOGIC; 
                           --clk_div4 : OUT STD_LOGIC; 
     clk_div8 : OUT STD_LOGIC); 
                           --clk_div64 : OUT STD_LOGIC); 
END fenpin;

  
ARCHITECTURE rtl OF fenpin is
SIGNAL count : STD_LOGIC_VECTOR(5 DOWNTO 0); 
BEGIN 
PROCESS(clk) 
BEGIN 
IF (clk'event AND clk='1')THEN 
IF(count="1111" ) THEN 
Count <= (OTHERS =>'0'); 
ELSE 
Count <= count +1; 
END IF ; 
END IF ; 

END PROCESS; 
               --clk_div2 <= count(0); 
               --clk_div4 <= count(1); 
clk_div8 <= count(2); 
               --clk_div64 <= count(3); 
END rtl;