qpsktiao.map.rpt

用VHDL语言实现QPSK调制功能和解调功能,

;     -- 4 input functions                    ; 7     ;
;     -- 3 input functions                    ; 7     ;
;     -- <=2 input functions                  ; 30    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 23    ;
;     -- arithmetic mode                      ; 21    ;
; Total registers                             ; 36    ;
; I/O pins                                    ; 26    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 26    ;
; Total fan-out                               ; 222   ;
; Average fan-out                             ; 2.09  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                       ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name       ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------+
; |qpsktiao                  ; 44 (1)            ; 36 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 26   ; 0            ; |qpsktiao                 ;
;    |clk_div:inst|          ; 13 (13)           ; 9 (9)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qpsktiao|clk_div:inst    ;
;    |counter8:inst1|        ; 8 (8)             ; 8 (8)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qpsktiao|counter8:inst1  ;
;    |fenpin:inst2|          ; 2 (2)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qpsktiao|fenpin:inst2    ;
;    |select4_1:inst3|       ; 3 (3)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qpsktiao|select4_1:inst3 ;
;    |seri_2:inst4|          ; 6 (6)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qpsktiao|seri_2:inst4    ;
;    |tiaopin:inst5|         ; 11 (11)           ; 8 (8)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |qpsktiao|tiaopin:inst5   ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 36    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |qpsktiao|select4_1:inst3|q[6] ;
; 6:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |qpsktiao|seri_2:inst4|n[0]    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+


+--------------------------------------+
; Source assignments for tiaopin:inst5 ;
+----------------+-------+------+------+
; Assignment     ; Value ; From ; To   ;
+----------------+-------+------+------+
; POWER_UP_LEVEL ; Low   ; -    ; m[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[5] ;
; POWER_UP_LEVEL ; Low   ; -    ; m[6] ;
+----------------+-------+------+------+


+--------------------------------------+
; Source assignments for seri_2:inst4  ;
+----------------+-------+------+------+
; Assignment     ; Value ; From ; To   ;
+----------------+-------+------+------+
; POWER_UP_LEVEL ; Low   ; -    ; n[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; n[1] ;
; POWER_UP_LEVEL ; Low   ; -    ; n[2] ;
+----------------+-------+------+------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri May 09 10:38:40 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qpsktiao -c qpsktiao
Info: Found 1 design units, including 1 entities, in source file qpsktiao.bdf
    Info: Found entity 1: qpsktiao
Info: Elaborating entity "qpsktiao" for the top level hierarchy
Warning: Port "q" of type counter8 and instance "inst1" is missing source signal
Warning: Using design file tiaopin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: tiaopin-rtl
    Info: Found entity 1: tiaopin
Info: Elaborating entity "tiaopin" for hierarchy "tiaopin:inst5"
Warning: Using design file clk_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clk_div-rel
    Info: Found entity 1: clk_div
Info: Elaborating entity "clk_div" for hierarchy "clk_div:inst"
Warning: Using design file fenpin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fenpin-rtl
    Info: Found entity 1: fenpin
Info: Elaborating entity "fenpin" for hierarchy "fenpin:inst2"
Warning: Using design file counter8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: counter8-rel
    Info: Found entity 1: counter8
Info: Elaborating entity "counter8" for hierarchy "counter8:inst1"
Warning: Using design file select4_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: select4_1-rel
    Info: Found entity 1: select4_1
Info: Elaborating entity "select4_1" for hierarchy "select4_1:inst3"
Warning: Using design file seri_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: seri_2-rel
    Info: Found entity 1: seri_2
Info: Elaborating entity "seri_2" for hierarchy "seri_2:inst4"
Warning: Reduced register "select4_1:inst3|q[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "select4_1:inst3|q[4]" merged to single register "select4_1:inst3|q[0]"
    Info: Duplicate register "select4_1:inst3|q[3]" merged to single register "select4_1:inst3|q[0]"
    Info: Duplicate register "select4_1:inst3|q[2]" merged to single register "select4_1:inst3|q[0]"
    Info: Duplicate register "select4_1:inst3|q[1]" merged to single register "select4_1:inst3|q[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "fenpin:inst2|count[0]" merged to single register "tiaopin:inst5|m[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "fenpin:inst2|count[1]" merged to single register "tiaopin:inst5|m[1]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "qm[7]" stuck at GND
Info: Implemented 74 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 21 output pins
    Info: Implemented 48 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Fri May 09 10:38:45 2008
    Info: Elapsed time: 00:00:07