counter8.vhd

来自「用VHDL语言实现QPSK调制功能和解调功能,」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter8 is
	port (clk,clr: in std_logic;
	      xx: in std_logic_vector(7 downto 0);
		  set: in std_logic;
		  en: in std_logic;
		  q: inout std_logic_vector(7 downto 0)
		   );
end counter8;

architecture rel of counter8 is
 --signal m :std_logic_vector(7 downto 0);
 begin
	process(clk,clr)
	begin
		if (clr='1') then q<=( others=>'0');
		elsif (clk'event and clk='1') then
		      if (set='1') then 
			      q<= xx;
			  elsif (en='1') then 
			      q<=q+1;
			  else q<=q;
			end if;
		end if;
end process;
end rel;