📄 tiaopin.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tiaopin is
port (clk: in std_logic;
tpin: out std_logic
);
end tiaopin;
architecture rtl of tiaopin is
begin
process(clk)
variable m : std_logic_vector(6 downto 0):="0000000";
begin
if (clk'event and clk='1') then
if (m="1000011") then
tpin<= '1';
m:="0000000";
else
m:=m+1;
tpin<='0';
end if;
end if;
end process;
end rtl;
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