📄 addr_gen.tan.qmsg

📁 用vhdl语言实现的中值滤波,硬件需要DE2板
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count_ray\[1\] register addr_count\[1\] 149.63 MHz 6.683 ns Internal " "Info: Clock \"clk\" has Internal fmax of 149.63 MHz between source register \"count_ray\[1\]\" and destination register \"addr_count\[1\]\" (period= 6.683 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.481 ns + Longest register register " "Info: + Longest register to register delay is 6.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_ray\[1\] 1 REG LC_X18_Y10_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y10_N2; Fanout = 4; REG Node = 'count_ray\[1\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { count_ray[1] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.454 ns) 0.870 ns LessThan~588 2 COMB LC_X18_Y10_N9 6 " "Info: 2: + IC(0.416 ns) + CELL(0.454 ns) = 0.870 ns; Loc. = LC_X18_Y10_N9; Fanout = 6; COMB Node = 'LessThan~588'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "0.870 ns" { count_ray[1] LessThan~588 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.975 ns) + CELL(0.454 ns) 2.299 ns addr_count\[2\]~1961 3 COMB LC_X18_Y12_N9 6 " "Info: 3: + IC(0.975 ns) + CELL(0.454 ns) = 2.299 ns; Loc. = LC_X18_Y12_N9; Fanout = 6; COMB Node = 'addr_count\[2\]~1961'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.429 ns" { LessThan~588 addr_count[2]~1961 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.454 ns) 3.641 ns addr_count\[1\]~254 4 COMB LC_X19_Y12_N1 1 " "Info: 4: + IC(0.888 ns) + CELL(0.454 ns) = 3.641 ns; Loc. = LC_X19_Y12_N1; Fanout = 1; COMB Node = 'addr_count\[1\]~254'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.342 ns" { addr_count[2]~1961 addr_count[1]~254 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.340 ns) 4.841 ns addr_count\[1\]~255 5 COMB LC_X18_Y12_N3 1 " "Info: 5: + IC(0.860 ns) + CELL(0.340 ns) = 4.841 ns; Loc. = LC_X18_Y12_N3; Fanout = 1; COMB Node = 'addr_count\[1\]~255'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.200 ns" { addr_count[1]~254 addr_count[1]~255 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.467 ns) 6.481 ns addr_count\[1\] 6 REG LC_X20_Y10_N5 6 " "Info: 6: + IC(1.173 ns) + CELL(0.467 ns) = 6.481 ns; Loc. = LC_X20_Y10_N5; Fanout = 6; REG Node = 'addr_count\[1\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.640 ns" { addr_count[1]~255 addr_count[1] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.169 ns 33.47 % " "Info: Total cell delay = 2.169 ns ( 33.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.312 ns 66.53 % " "Info: Total interconnect delay = 4.312 ns ( 66.53 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "6.481 ns" { count_ray[1] LessThan~588 addr_count[2]~1961 addr_count[1]~254 addr_count[1]~255 addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.481 ns" { count_ray[1] LessThan~588 addr_count[2]~1961 addr_count[1]~254 addr_count[1]~255 addr_count[1] } { 0.000ns 0.416ns 0.975ns 0.888ns 0.860ns 1.173ns } { 0.000ns 0.454ns 0.454ns 0.454ns 0.340ns 0.467ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.138 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 64 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 64; CLK Node = 'clk'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { clk } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns addr_count\[1\] 2 REG LC_X20_Y10_N5 6 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X20_Y10_N5; Fanout = 6; REG Node = 'addr_count\[1\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.008 ns" { clk addr_count[1] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 addr_count[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.138 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 64 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 64; CLK Node = 'clk'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { clk } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns count_ray\[1\] 2 REG LC_X18_Y10_N2 4 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X18_Y10_N2; Fanout = 4; REG Node = 'count_ray\[1\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.008 ns" { clk count_ray[1] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk count_ray[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 count_ray[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 addr_count[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk count_ray[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 count_ray[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "6.481 ns" { count_ray[1] LessThan~588 addr_count[2]~1961 addr_count[1]~254 addr_count[1]~255 addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.481 ns" { count_ray[1] LessThan~588 addr_count[2]~1961 addr_count[1]~254 addr_count[1]~255 addr_count[1] } { 0.000ns 0.416ns 0.975ns 0.888ns 0.860ns 1.173ns } { 0.000ns 0.454ns 0.454ns 0.454ns 0.340ns 0.467ns } } } { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 addr_count[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk count_ray[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 count_ray[1] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "old_addr_count\[8\] rst clk 2.059 ns register " "Info: tsu for register \"old_addr_count\[8\]\" (data pin = \"rst\", clock pin = \"clk\") is 2.059 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.168 ns + Longest pin register " "Info: + Longest pin to register delay is 4.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rst 1 PIN PIN_66 52 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 52; PIN Node = 'rst'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { rst } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.225 ns) 2.275 ns old_addr_count\[12\]~0 2 COMB LC_X19_Y12_N2 13 " "Info: 2: + IC(0.920 ns) + CELL(0.225 ns) = 2.275 ns; Loc. = LC_X19_Y12_N2; Fanout = 13; COMB Node = 'old_addr_count\[12\]~0'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.145 ns" { rst old_addr_count[12]~0 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.667 ns) 4.168 ns old_addr_count\[8\] 3 REG LC_X20_Y11_N6 8 " "Info: 3: + IC(1.226 ns) + CELL(0.667 ns) = 4.168 ns; Loc. = LC_X20_Y11_N6; Fanout = 8; REG Node = 'old_addr_count\[8\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.893 ns" { old_addr_count[12]~0 old_addr_count[8] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.022 ns 48.51 % " "Info: Total cell delay = 2.022 ns ( 48.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.146 ns 51.49 % " "Info: Total interconnect delay = 2.146 ns ( 51.49 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "4.168 ns" { rst old_addr_count[12]~0 old_addr_count[8] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "4.168 ns" { rst rst~out0 old_addr_count[12]~0 old_addr_count[8] } { 0.000ns 0.000ns 0.920ns 1.226ns } { 0.000ns 1.130ns 0.225ns 0.667ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.138 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 64 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 64; CLK Node = 'clk'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { clk } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns old_addr_count\[8\] 2 REG LC_X20_Y11_N6 8 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X20_Y11_N6; Fanout = 8; REG Node = 'old_addr_count\[8\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.008 ns" { clk old_addr_count[8] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk old_addr_count[8] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 old_addr_count[8] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "4.168 ns" { rst old_addr_count[12]~0 old_addr_count[8] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "4.168 ns" { rst rst~out0 old_addr_count[12]~0 old_addr_count[8] } { 0.000ns 0.000ns 0.920ns 1.226ns } { 0.000ns 1.130ns 0.225ns 0.667ns } } } { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk old_addr_count[8] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 old_addr_count[8] } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk addr\[7\] addr\[7\]~reg0 5.645 ns register " "Info: tco from clock \"clk\" to destination pin \"addr\[7\]\" through register \"addr\[7\]~reg0\" is 5.645 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.138 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 64 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 64; CLK Node = 'clk'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { clk } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.547 ns) 2.138 ns addr\[7\]~reg0 2 REG LC_X21_Y11_N1 1 " "Info: 2: + IC(0.461 ns) + CELL(0.547 ns) = 2.138 ns; Loc. = LC_X21_Y11_N1; Fanout = 1; REG Node = 'addr\[7\]~reg0'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.008 ns" { clk addr[7]~reg0 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 136 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.44 % " "Info: Total cell delay = 1.677 ns ( 78.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.461 ns 21.56 % " "Info: Total interconnect delay = 0.461 ns ( 21.56 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk addr[7]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 addr[7]~reg0 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 136 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.334 ns + Longest register pin " "Info: + Longest register to pin delay is 3.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addr\[7\]~reg0 1 REG LC_X21_Y11_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N1; Fanout = 1; REG Node = 'addr\[7\]~reg0'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { addr[7]~reg0 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 136 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.634 ns) 3.334 ns addr\[7\] 2 PIN PIN_68 0 " "Info: 2: + IC(1.700 ns) + CELL(1.634 ns) = 3.334 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'addr\[7\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "3.334 ns" { addr[7]~reg0 addr[7] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 49.01 % " "Info: Total cell delay = 1.634 ns ( 49.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 50.99 % " "Info: Total interconnect delay = 1.700 ns ( 50.99 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "3.334 ns" { addr[7]~reg0 addr[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.334 ns" { addr[7]~reg0 addr[7] } { 0.000ns 1.700ns } { 0.000ns 1.634ns } } }  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.138 ns" { clk addr[7]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.138 ns" { clk clk~out0 addr[7]~reg0 } { 0.000ns 0.000ns 0.461ns } { 0.000ns 1.130ns 0.547ns } } } { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "3.334 ns" { addr[7]~reg0 addr[7] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.334 ns" { addr[7]~reg0 addr[7] } { 0.000ns 1.700ns } { 0.000ns 1.634ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "old_addr_count\[1\] rst clk -1.140 ns register " "Info: th for register \"old_addr_count\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is -1.140 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.139 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 64 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 64; CLK Node = 'clk'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { clk } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.547 ns) 2.139 ns old_addr_count\[1\] 2 REG LC_X19_Y12_N1 6 " "Info: 2: + IC(0.462 ns) + CELL(0.547 ns) = 2.139 ns; Loc. = LC_X19_Y12_N1; Fanout = 6; REG Node = 'old_addr_count\[1\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.009 ns" { clk old_addr_count[1] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.40 % " "Info: Total cell delay = 1.677 ns ( 78.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns 21.60 % " "Info: Total interconnect delay = 0.462 ns ( 21.60 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.139 ns" { clk old_addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 old_addr_count[1] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.291 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.291 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rst 1 PIN PIN_66 52 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 52; PIN Node = 'rst'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "" { rst } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.225 ns) 2.275 ns old_addr_count\[12\]~0 2 COMB LC_X19_Y12_N2 13 " "Info: 2: + IC(0.920 ns) + CELL(0.225 ns) = 2.275 ns; Loc. = LC_X19_Y12_N2; Fanout = 13; COMB Node = 'old_addr_count\[12\]~0'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.145 ns" { rst old_addr_count[12]~0 } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.667 ns) 3.291 ns old_addr_count\[1\] 3 REG LC_X19_Y12_N1 6 " "Info: 3: + IC(0.349 ns) + CELL(0.667 ns) = 3.291 ns; Loc. = LC_X19_Y12_N1; Fanout = 6; REG Node = 'old_addr_count\[1\]'" {  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "1.016 ns" { old_addr_count[12]~0 old_addr_count[1] } "NODE_NAME" } "" } } { "addr_gen.v" "" { Text "G:/laurie/addr_gen/addr_gen/addr_gen.v" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.022 ns 61.44 % " "Info: Total cell delay = 2.022 ns ( 61.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.269 ns 38.56 % " "Info: Total interconnect delay = 1.269 ns ( 38.56 % )" {  } {  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "3.291 ns" { rst old_addr_count[12]~0 old_addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.291 ns" { rst rst~out0 old_addr_count[12]~0 old_addr_count[1] } { 0.000ns 0.000ns 0.920ns 0.349ns } { 0.000ns 1.130ns 0.225ns 0.667ns } } }  } 0}  } { { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "2.139 ns" { clk old_addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "2.139 ns" { clk clk~out0 old_addr_count[1] } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.547ns } } } { "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" "" { Report "G:/laurie/addr_gen/addr_gen/db/addr_gen_cmp.qrpt" Compiler "addr_gen" "UNKNOWN" "V1" "G:/laurie/addr_gen/addr_gen/db/addr_gen.quartus_db" { Floorplan "G:/laurie/addr_gen/addr_gen/" "" "3.291 ns" { rst old_addr_count[12]~0 old_addr_count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.291 ns" { rst rst~out0 old_addr_count[12]~0 old_addr_count[1] } { 0.000ns 0.000ns 0.920ns 0.349ns } { 0.000ns 1.130ns 0.225ns 0.667ns } } }  } 0}
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