led_scan.fit.qmsg

用DE2板子实现的控制64乘64点阵LED的点亮,硬件需要de2板及led点阵

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.939 ns memory register " "Info: Estimated most critical path is memory to register delay of 8.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.088 ns) 0.088 ns rom_green:inst2\|altsyncram:altsyncram_component\|altsyncram_d671:auto_generated\|ram_block1a5 1 MEM M4K_X26_Y29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X26_Y29; Fanout = 1; MEM Node = 'rom_green:inst2\|altsyncram:altsyncram_component\|altsyncram_d671:auto_generated\|ram_block1a5'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|ram_block1a5 } "NODE_NAME" } } { "db/altsyncram_d671.tdf" "" { Text "E:/lianxi/integrity/db/altsyncram_d671.tdf" 145 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.482 ns) + CELL(0.150 ns) 1.720 ns rom_green:inst2\|altsyncram:altsyncram_component\|altsyncram_d671:auto_generated\|mux_kib:mux2\|result_node\[5\]~454 2 COMB LAB_X31_Y22 1 " "Info: 2: + IC(1.482 ns) + CELL(0.150 ns) = 1.720 ns; Loc. = LAB_X31_Y22; Fanout = 1; COMB Node = 'rom_green:inst2\|altsyncram:altsyncram_component\|altsyncram_d671:auto_generated\|mux_kib:mux2\|result_node\[5\]~454'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.632 ns" { rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|ram_block1a5 rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2|result_node[5]~454 } "NODE_NAME" } } { "db/mux_kib.tdf" "" { Text "E:/lianxi/integrity/db/mux_kib.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.271 ns) 2.281 ns rom_green:inst2\|altsyncram:altsyncram_component\|altsyncram_d671:auto_generated\|mux_kib:mux2\|result_node\[5\]~455 3 COMB LAB_X31_Y22 55 " "Info: 3: + IC(0.290 ns) + CELL(0.271 ns) = 2.281 ns; Loc. = LAB_X31_Y22; Fanout = 55; COMB Node = 'rom_green:inst2\|altsyncram:altsyncram_component\|altsyncram_d671:auto_generated\|mux_kib:mux2\|result_node\[5\]~455'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2|result_node[5]~454 rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2|result_node[5]~455 } "NODE_NAME" } } { "db/mux_kib.tdf" "" { Text "E:/lianxi/integrity/db/mux_kib.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.526 ns) + CELL(0.275 ns) 4.082 ns CUS_r_CORRECTION:inst3\|Mux5~617 4 COMB LAB_X41_Y24 1 " "Info: 4: + IC(1.526 ns) + CELL(0.275 ns) = 4.082 ns; Loc. = LAB_X41_Y24; Fanout = 1; COMB Node = 'CUS_r_CORRECTION:inst3\|Mux5~617'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.801 ns" { rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2|result_node[5]~455 CUS_r_CORRECTION:inst3|Mux5~617 } "NODE_NAME" } } { "CUS_r_CORRECTION .vhd" "" { Text "E:/lianxi/integrity/CUS_r_CORRECTION .vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 4.647 ns CUS_r_CORRECTION:inst3\|Mux5~618 5 COMB LAB_X41_Y24 1 " "Info: 5: + IC(0.415 ns) + CELL(0.150 ns) = 4.647 ns; Loc. = LAB_X41_Y24; Fanout = 1; COMB Node = 'CUS_r_CORRECTION:inst3\|Mux5~618'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { CUS_r_CORRECTION:inst3|Mux5~617 CUS_r_CORRECTION:inst3|Mux5~618 } "NODE_NAME" } } { "CUS_r_CORRECTION .vhd" "" { Text "E:/lianxi/integrity/CUS_r_CORRECTION .vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 5.212 ns CUS_r_CORRECTION:inst3\|Mux5~620 6 COMB LAB_X41_Y24 1 " "Info: 6: + IC(0.290 ns) + CELL(0.275 ns) = 5.212 ns; Loc. = LAB_X41_Y24; Fanout = 1; COMB Node = 'CUS_r_CORRECTION:inst3\|Mux5~620'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { CUS_r_CORRECTION:inst3|Mux5~618 CUS_r_CORRECTION:inst3|Mux5~620 } "NODE_NAME" } } { "CUS_r_CORRECTION .vhd" "" { Text "E:/lianxi/integrity/CUS_r_CORRECTION .vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.419 ns) 6.267 ns CUS_r_CORRECTION:inst3\|Mux5~627 7 COMB LAB_X41_Y21 1 " "Info: 7: + IC(0.636 ns) + CELL(0.419 ns) = 6.267 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'CUS_r_CORRECTION:inst3\|Mux5~627'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.055 ns" { CUS_r_CORRECTION:inst3|Mux5~620 CUS_r_CORRECTION:inst3|Mux5~627 } "NODE_NAME" } } { "CUS_r_CORRECTION .vhd" "" { Text "E:/lianxi/integrity/CUS_r_CORRECTION .vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.271 ns) 6.828 ns CUS_r_CORRECTION:inst3\|Mux5~634 8 COMB LAB_X41_Y21 1 " "Info: 8: + IC(0.290 ns) + CELL(0.271 ns) = 6.828 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'CUS_r_CORRECTION:inst3\|Mux5~634'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { CUS_r_CORRECTION:inst3|Mux5~627 CUS_r_CORRECTION:inst3|Mux5~634 } "NODE_NAME" } } { "CUS_r_CORRECTION .vhd" "" { Text "E:/lianxi/integrity/CUS_r_CORRECTION .vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.393 ns) 7.636 ns LED_SCAN:inst\|LessThan7~109 9 COMB LAB_X41_Y21 1 " "Info: 9: + IC(0.415 ns) + CELL(0.393 ns) = 7.636 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|LessThan7~109'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.808 ns" { CUS_r_CORRECTION:inst3|Mux5~634 LED_SCAN:inst|LessThan7~109 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.707 ns LED_SCAN:inst\|LessThan7~111 10 COMB LAB_X41_Y21 1 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 7.707 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|LessThan7~111'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LED_SCAN:inst|LessThan7~109 LED_SCAN:inst|LessThan7~111 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.778 ns LED_SCAN:inst\|LessThan7~113 11 COMB LAB_X41_Y21 1 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 7.778 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|LessThan7~113'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LED_SCAN:inst|LessThan7~111 LED_SCAN:inst|LessThan7~113 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.849 ns LED_SCAN:inst\|LessThan7~115 12 COMB LAB_X41_Y21 1 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 7.849 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|LessThan7~115'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LED_SCAN:inst|LessThan7~113 LED_SCAN:inst|LessThan7~115 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.920 ns LED_SCAN:inst\|LessThan7~117 13 COMB LAB_X41_Y21 1 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 7.920 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|LessThan7~117'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { LED_SCAN:inst|LessThan7~115 LED_SCAN:inst|LessThan7~117 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.330 ns LED_SCAN:inst\|LessThan7~118 14 COMB LAB_X41_Y21 1 " "Info: 14: + IC(0.000 ns) + CELL(0.410 ns) = 8.330 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|LessThan7~118'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LED_SCAN:inst|LessThan7~117 LED_SCAN:inst|LessThan7~118 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.398 ns) 8.855 ns LED_SCAN:inst\|iDG~2 15 COMB LAB_X41_Y21 1 " "Info: 15: + IC(0.127 ns) + CELL(0.398 ns) = 8.855 ns; Loc. = LAB_X41_Y21; Fanout = 1; COMB Node = 'LED_SCAN:inst\|iDG~2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.525 ns" { LED_SCAN:inst|LessThan7~118 LED_SCAN:inst|iDG~2 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.939 ns LED_SCAN:inst\|iDG 16 REG LAB_X41_Y21 1 " "Info: 16: + IC(0.000 ns) + CELL(0.084 ns) = 8.939 ns; Loc. = LAB_X41_Y21; Fanout = 1; REG Node = 'LED_SCAN:inst\|iDG'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { LED_SCAN:inst|iDG~2 LED_SCAN:inst|iDG } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.468 ns ( 38.80 % ) " "Info: Total cell delay = 3.468 ns ( 38.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.471 ns ( 61.20 % ) " "Info: Total interconnect delay = 5.471 ns ( 61.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.939 ns" { rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|ram_block1a5 rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2|result_node[5]~454 rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2|result_node[5]~455 CUS_r_CORRECTION:inst3|Mux5~617 CUS_r_CORRECTION:inst3|Mux5~618 CUS_r_CORRECTION:inst3|Mux5~620 CUS_r_CORRECTION:inst3|Mux5~627 CUS_r_CORRECTION:inst3|Mux5~634 LED_SCAN:inst|LessThan7~109 LED_SCAN:inst|LessThan7~111 LED_SCAN:inst|LessThan7~113 LED_SCAN:inst|LessThan7~115 LED_SCAN:inst|LessThan7~117 LED_SCAN:inst|LessThan7~118 LED_SCAN:inst|iDG~2 LED_SCAN:inst|iDG } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 5 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 5%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x22_y12 x32_y23 " "Info: The peak interconnect region extends from location x22_y12 to location x32_y23" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:07 " "Info: Fitter routing operations ending: elapsed time is 00:00:07" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oe 0 " "Info: Pin \"oe\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "dg 0 " "Info: Pin \"dg\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "dr 0 " "Info: Pin \"dr\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk 0 " "Info: Pin \"clk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "stb 0 " "Info: Pin \"stb\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sc\[3\] 0 " "Info: Pin \"sc\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sc\[2\] 0 " "Info: Pin \"sc\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sc\[1\] 0 " "Info: Pin \"sc\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sc\[0\] 0 " "Info: Pin \"sc\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 11 15:35:08 2008 " "Info: Processing ended: Fri Jan 11 15:35:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Info: Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/lianxi/integrity/led_scan.fit.smsg " "Info: Generated suppressed messages file E:/lianxi/integrity/led_scan.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}