led_scan.tan.qmsg

用DE2板子实现的控制64乘64点阵LED的点亮,硬件需要de2板及led点阵

{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50m dr LED_SCAN:inst\|iDR 10.531 ns register " "Info: tco from clock \"clk_50m\" to destination pin \"dr\" through register \"LED_SCAN:inst\|iDR\" is 10.531 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50m source 5.088 ns + Longest register " "Info: + Longest clock path from clock \"clk_50m\" to source register is 5.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_50m 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50m'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_50m } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_50m~clkctrl 2 COMB CLKCTRL_G2 838 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 838; COMB Node = 'clk_50m~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_50m clk_50m~clkctrl } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.787 ns) 2.940 ns LED_SCAN:inst\|CLK_1M 3 REG LCFF_X64_Y19_N31 3 " "Info: 3: + IC(1.036 ns) + CELL(0.787 ns) = 2.940 ns; Loc. = LCFF_X64_Y19_N31; Fanout = 3; REG Node = 'LED_SCAN:inst\|CLK_1M'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.823 ns" { clk_50m~clkctrl LED_SCAN:inst|CLK_1M } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.590 ns) + CELL(0.000 ns) 3.530 ns LED_SCAN:inst\|CLK_1M~clkctrl 4 COMB CLKCTRL_G6 45 " "Info: 4: + IC(0.590 ns) + CELL(0.000 ns) = 3.530 ns; Loc. = CLKCTRL_G6; Fanout = 45; COMB Node = 'LED_SCAN:inst\|CLK_1M~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.590 ns" { LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 5.088 ns LED_SCAN:inst\|iDR 5 REG LCFF_X32_Y22_N29 1 " "Info: 5: + IC(1.021 ns) + CELL(0.537 ns) = 5.088 ns; Loc. = LCFF_X32_Y22_N29; Fanout = 1; REG Node = 'LED_SCAN:inst\|iDR'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|iDR } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.66 % ) " "Info: Total cell delay = 2.323 ns ( 45.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.765 ns ( 54.34 % ) " "Info: Total interconnect delay = 2.765 ns ( 54.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.088 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|iDR } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.088 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|iDR } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 152 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.193 ns + Longest register pin " "Info: + Longest register to pin delay is 5.193 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED_SCAN:inst\|iDR 1 REG LCFF_X32_Y22_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y22_N29; Fanout = 1; REG Node = 'LED_SCAN:inst\|iDR'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LED_SCAN:inst|iDR } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.541 ns) + CELL(2.652 ns) 5.193 ns dr 2 PIN PIN_M20 0 " "Info: 2: + IC(2.541 ns) + CELL(2.652 ns) = 5.193 ns; Loc. = PIN_M20; Fanout = 0; PIN Node = 'dr'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.193 ns" { LED_SCAN:inst|iDR dr } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 184 480 656 200 "dr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.652 ns ( 51.07 % ) " "Info: Total cell delay = 2.652 ns ( 51.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.541 ns ( 48.93 % ) " "Info: Total interconnect delay = 2.541 ns ( 48.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.193 ns" { LED_SCAN:inst|iDR dr } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.193 ns" { LED_SCAN:inst|iDR dr } { 0.000ns 2.541ns } { 0.000ns 2.652ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.088 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|iDR } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.088 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|iDR } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.193 ns" { LED_SCAN:inst|iDR dr } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.193 ns" { LED_SCAN:inst|iDR dr } { 0.000ns 2.541ns } { 0.000ns 2.652ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 11 15:35:35 2008 " "Info: Processing ended: Fri Jan 11 15:35:35 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}