📄 led_scan.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_50m " "Info: Assuming node \"clk_50m\" is an undefined clock" { } { { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_50m" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "LED_SCAN:inst\|CLK_1M " "Info: Detected ripple clock \"LED_SCAN:inst\|CLK_1M\" as buffer" { } { { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LED_SCAN:inst\|CLK_1M" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50m register LED_SCAN:inst\|BIT_SHIFT_COUNT\[6\] register LED_SCAN:inst\|READADDR_RAM\[7\] 77.15 MHz 12.962 ns Internal " "Info: Clock \"clk_50m\" has Internal fmax of 77.15 MHz between source register \"LED_SCAN:inst\|BIT_SHIFT_COUNT\[6\]\" and destination register \"LED_SCAN:inst\|READADDR_RAM\[7\]\" (period= 12.962 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.270 ns + Longest register register " "Info: + Longest register to register delay is 6.270 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED_SCAN:inst\|BIT_SHIFT_COUNT\[6\] 1 REG LCFF_X53_Y14_N25 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X53_Y14_N25; Fanout = 20; REG Node = 'LED_SCAN:inst\|BIT_SHIFT_COUNT\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LED_SCAN:inst|BIT_SHIFT_COUNT[6] } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 104 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.437 ns) 1.267 ns LED_SCAN:inst\|Add9~168 2 COMB LCCOMB_X54_Y13_N20 1 " "Info: 2: + IC(0.830 ns) + CELL(0.437 ns) = 1.267 ns; Loc. = LCCOMB_X54_Y13_N20; Fanout = 1; COMB Node = 'LED_SCAN:inst\|Add9~168'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.267 ns" { LED_SCAN:inst|BIT_SHIFT_COUNT[6] LED_SCAN:inst|Add9~168 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 84 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.438 ns) 2.156 ns LED_SCAN:inst\|Add14~227 3 COMB LCCOMB_X55_Y13_N6 1 " "Info: 3: + IC(0.451 ns) + CELL(0.438 ns) = 2.156 ns; Loc. = LCCOMB_X55_Y13_N6; Fanout = 1; COMB Node = 'LED_SCAN:inst\|Add14~227'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.889 ns" { LED_SCAN:inst|Add9~168 LED_SCAN:inst|Add14~227 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.150 ns) 2.543 ns LED_SCAN:inst\|Add14~228 4 COMB LCCOMB_X55_Y13_N0 2 " "Info: 4: + IC(0.237 ns) + CELL(0.150 ns) = 2.543 ns; Loc. = LCCOMB_X55_Y13_N0; Fanout = 2; COMB Node = 'LED_SCAN:inst\|Add14~228'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.387 ns" { LED_SCAN:inst|Add14~227 LED_SCAN:inst|Add14~228 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.414 ns) 3.656 ns LED_SCAN:inst\|Add14~230 5 COMB LCCOMB_X53_Y13_N20 2 " "Info: 5: + IC(0.699 ns) + CELL(0.414 ns) = 3.656 ns; Loc. = LCCOMB_X53_Y13_N20; Fanout = 2; COMB Node = 'LED_SCAN:inst\|Add14~230'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.113 ns" { LED_SCAN:inst|Add14~228 LED_SCAN:inst|Add14~230 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 4.066 ns LED_SCAN:inst\|Add14~233 6 COMB LCCOMB_X53_Y13_N22 1 " "Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 4.066 ns; Loc. = LCCOMB_X53_Y13_N22; Fanout = 1; COMB Node = 'LED_SCAN:inst\|Add14~233'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { LED_SCAN:inst|Add14~230 LED_SCAN:inst|Add14~233 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.845 ns) + CELL(0.275 ns) 6.186 ns LED_SCAN:inst\|READADDR_RAM~1609 7 COMB LCCOMB_X30_Y20_N4 1 " "Info: 7: + IC(1.845 ns) + CELL(0.275 ns) = 6.186 ns; Loc. = LCCOMB_X30_Y20_N4; Fanout = 1; COMB Node = 'LED_SCAN:inst\|READADDR_RAM~1609'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.120 ns" { LED_SCAN:inst|Add14~233 LED_SCAN:inst|READADDR_RAM~1609 } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.270 ns LED_SCAN:inst\|READADDR_RAM\[7\] 8 REG LCFF_X30_Y20_N5 64 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 6.270 ns; Loc. = LCFF_X30_Y20_N5; Fanout = 64; REG Node = 'LED_SCAN:inst\|READADDR_RAM\[7\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { LED_SCAN:inst|READADDR_RAM~1609 LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.208 ns ( 35.22 % ) " "Info: Total cell delay = 2.208 ns ( 35.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.062 ns ( 64.78 % ) " "Info: Total interconnect delay = 4.062 ns ( 64.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.270 ns" { LED_SCAN:inst|BIT_SHIFT_COUNT[6] LED_SCAN:inst|Add9~168 LED_SCAN:inst|Add14~227 LED_SCAN:inst|Add14~228 LED_SCAN:inst|Add14~230 LED_SCAN:inst|Add14~233 LED_SCAN:inst|READADDR_RAM~1609 LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.270 ns" { LED_SCAN:inst|BIT_SHIFT_COUNT[6] LED_SCAN:inst|Add9~168 LED_SCAN:inst|Add14~227 LED_SCAN:inst|Add14~228 LED_SCAN:inst|Add14~230 LED_SCAN:inst|Add14~233 LED_SCAN:inst|READADDR_RAM~1609 LED_SCAN:inst|READADDR_RAM[7] } { 0.000ns 0.830ns 0.451ns 0.237ns 0.699ns 0.000ns 1.845ns 0.000ns } { 0.000ns 0.437ns 0.438ns 0.150ns 0.414ns 0.410ns 0.275ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.003 ns - Smallest " "Info: - Smallest clock skew is 0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50m destination 5.093 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50m\" to destination register is 5.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_50m 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50m'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_50m } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_50m~clkctrl 2 COMB CLKCTRL_G2 838 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 838; COMB Node = 'clk_50m~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_50m clk_50m~clkctrl } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.787 ns) 2.940 ns LED_SCAN:inst\|CLK_1M 3 REG LCFF_X64_Y19_N31 3 " "Info: 3: + IC(1.036 ns) + CELL(0.787 ns) = 2.940 ns; Loc. = LCFF_X64_Y19_N31; Fanout = 3; REG Node = 'LED_SCAN:inst\|CLK_1M'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.823 ns" { clk_50m~clkctrl LED_SCAN:inst|CLK_1M } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.590 ns) + CELL(0.000 ns) 3.530 ns LED_SCAN:inst\|CLK_1M~clkctrl 4 COMB CLKCTRL_G6 45 " "Info: 4: + IC(0.590 ns) + CELL(0.000 ns) = 3.530 ns; Loc. = CLKCTRL_G6; Fanout = 45; COMB Node = 'LED_SCAN:inst\|CLK_1M~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.590 ns" { LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.537 ns) 5.093 ns LED_SCAN:inst\|READADDR_RAM\[7\] 5 REG LCFF_X30_Y20_N5 64 " "Info: 5: + IC(1.026 ns) + CELL(0.537 ns) = 5.093 ns; Loc. = LCFF_X30_Y20_N5; Fanout = 64; REG Node = 'LED_SCAN:inst\|READADDR_RAM\[7\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.563 ns" { LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 68 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.61 % ) " "Info: Total cell delay = 2.323 ns ( 45.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.770 ns ( 54.39 % ) " "Info: Total interconnect delay = 2.770 ns ( 54.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.093 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.093 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50m source 5.090 ns - Longest register " "Info: - Longest clock path from clock \"clk_50m\" to source register is 5.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_50m 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50m'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_50m } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_50m~clkctrl 2 COMB CLKCTRL_G2 838 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 838; COMB Node = 'clk_50m~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_50m clk_50m~clkctrl } "NODE_NAME" } } { "led_control.bdf" "" { Schematic "E:/lianxi/integrity/led_control.bdf" { { 72 0 168 88 "clk_50m" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.787 ns) 2.940 ns LED_SCAN:inst\|CLK_1M 3 REG LCFF_X64_Y19_N31 3 " "Info: 3: + IC(1.036 ns) + CELL(0.787 ns) = 2.940 ns; Loc. = LCFF_X64_Y19_N31; Fanout = 3; REG Node = 'LED_SCAN:inst\|CLK_1M'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.823 ns" { clk_50m~clkctrl LED_SCAN:inst|CLK_1M } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.590 ns) + CELL(0.000 ns) 3.530 ns LED_SCAN:inst\|CLK_1M~clkctrl 4 COMB CLKCTRL_G6 45 " "Info: 4: + IC(0.590 ns) + CELL(0.000 ns) = 3.530 ns; Loc. = CLKCTRL_G6; Fanout = 45; COMB Node = 'LED_SCAN:inst\|CLK_1M~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.590 ns" { LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 5.090 ns LED_SCAN:inst\|BIT_SHIFT_COUNT\[6\] 5 REG LCFF_X53_Y14_N25 20 " "Info: 5: + IC(1.023 ns) + CELL(0.537 ns) = 5.090 ns; Loc. = LCFF_X53_Y14_N25; Fanout = 20; REG Node = 'LED_SCAN:inst\|BIT_SHIFT_COUNT\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } "NODE_NAME" } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 104 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.64 % ) " "Info: Total cell delay = 2.323 ns ( 45.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.767 ns ( 54.36 % ) " "Info: Total interconnect delay = 2.767 ns ( 54.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.090 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.090 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.093 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.093 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.090 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.090 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 104 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 68 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 104 -1 0 } } { "led_scan.vhd" "" { Text "E:/lianxi/integrity/led_scan.vhd" 68 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.270 ns" { LED_SCAN:inst|BIT_SHIFT_COUNT[6] LED_SCAN:inst|Add9~168 LED_SCAN:inst|Add14~227 LED_SCAN:inst|Add14~228 LED_SCAN:inst|Add14~230 LED_SCAN:inst|Add14~233 LED_SCAN:inst|READADDR_RAM~1609 LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.270 ns" { LED_SCAN:inst|BIT_SHIFT_COUNT[6] LED_SCAN:inst|Add9~168 LED_SCAN:inst|Add14~227 LED_SCAN:inst|Add14~228 LED_SCAN:inst|Add14~230 LED_SCAN:inst|Add14~233 LED_SCAN:inst|READADDR_RAM~1609 LED_SCAN:inst|READADDR_RAM[7] } { 0.000ns 0.830ns 0.451ns 0.237ns 0.699ns 0.000ns 1.845ns 0.000ns } { 0.000ns 0.437ns 0.438ns 0.150ns 0.414ns 0.410ns 0.275ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.093 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.093 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|READADDR_RAM[7] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.090 ns" { clk_50m clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.090 ns" { clk_50m clk_50m~combout clk_50m~clkctrl LED_SCAN:inst|CLK_1M LED_SCAN:inst|CLK_1M~clkctrl LED_SCAN:inst|BIT_SHIFT_COUNT[6] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.590ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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