led_scan.hier_info

用DE2板子实现的控制64乘64点阵LED的点亮,硬件需要de2板及led点阵

|led_control
oe <= LED_SCAN:inst.OE
clk_50m => LED_SCAN:inst.CLK_50M
dg <= LED_SCAN:inst.DG
dr <= LED_SCAN:inst.DR
clk <= LED_SCAN:inst.CLK
stb <= LED_SCAN:inst.STB
sc[0] <= LED_SCAN:inst.SC[0]
sc[1] <= LED_SCAN:inst.SC[1]
sc[2] <= LED_SCAN:inst.SC[2]
sc[3] <= LED_SCAN:inst.SC[3]


|led_control|LED_SCAN:inst
CLK_50M => CLK_1M.CLK
CLK_50M => DIV_COUNT[0].CLK
CLK_50M => DIV_COUNT[1].CLK
CLK_50M => DIV_COUNT[2].CLK
CLK_50M => DIV_COUNT[3].CLK
CLK_50M => DIV_COUNT[4].CLK
CLK_50M => READCLK_RAM.DATAIN
DGIN[0] => LessThan7.IN8
DGIN[1] => LessThan7.IN7
DGIN[2] => LessThan7.IN6
DGIN[3] => LessThan7.IN5
DGIN[4] => LessThan7.IN4
DGIN[5] => LessThan7.IN3
DGIN[6] => LessThan7.IN2
DGIN[7] => LessThan7.IN1
DRIN[0] => LessThan8.IN8
DRIN[1] => LessThan8.IN7
DRIN[2] => LessThan8.IN6
DRIN[3] => LessThan8.IN5
DRIN[4] => LessThan8.IN4
DRIN[5] => LessThan8.IN3
DRIN[6] => LessThan8.IN2
DRIN[7] => LessThan8.IN1
READCLK_RAM <= CLK_50M.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[0] <= READADDR_RAM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[1] <= READADDR_RAM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[2] <= READADDR_RAM[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[3] <= READADDR_RAM[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[4] <= READADDR_RAM[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[5] <= READADDR_RAM[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[6] <= READADDR_RAM[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[7] <= READADDR_RAM[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[8] <= READADDR_RAM[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[9] <= READADDR_RAM[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[10] <= READADDR_RAM[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[11] <= READADDR_RAM[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[12] <= zhen[0].DB_MAX_OUTPUT_PORT_TYPE
READADDR_RAM[13] <= zhen[1].DB_MAX_OUTPUT_PORT_TYPE
OE <= OE~reg0.DB_MAX_OUTPUT_PORT_TYPE
DG <= iDG.DB_MAX_OUTPUT_PORT_TYPE
DR <= iDR.DB_MAX_OUTPUT_PORT_TYPE
CLK <= CLK~0.DB_MAX_OUTPUT_PORT_TYPE
STB <= STB~reg0.DB_MAX_OUTPUT_PORT_TYPE
SC[0] <= iSC[0].DB_MAX_OUTPUT_PORT_TYPE
SC[1] <= iSC[1].DB_MAX_OUTPUT_PORT_TYPE
SC[2] <= iSC[2].DB_MAX_OUTPUT_PORT_TYPE
SC[3] <= iSC[3].DB_MAX_OUTPUT_PORT_TYPE


|led_control|CUS_r_CORRECTION:inst3
dateg[0] => Mux0.IN263
dateg[0] => Mux1.IN263
dateg[0] => Mux2.IN263
dateg[0] => Mux3.IN263
dateg[0] => Mux4.IN263
dateg[0] => Mux5.IN263
dateg[0] => Mux6.IN263
dateg[0] => Mux7.IN263
dateg[1] => Mux0.IN262
dateg[1] => Mux1.IN262
dateg[1] => Mux2.IN262
dateg[1] => Mux3.IN262
dateg[1] => Mux4.IN262
dateg[1] => Mux5.IN262
dateg[1] => Mux6.IN262
dateg[1] => Mux7.IN262
dateg[2] => Mux0.IN261
dateg[2] => Mux1.IN261
dateg[2] => Mux2.IN261
dateg[2] => Mux3.IN261
dateg[2] => Mux4.IN261
dateg[2] => Mux5.IN261
dateg[2] => Mux6.IN261
dateg[2] => Mux7.IN261
dateg[3] => Mux0.IN260
dateg[3] => Mux1.IN260
dateg[3] => Mux2.IN260
dateg[3] => Mux3.IN260
dateg[3] => Mux4.IN260
dateg[3] => Mux5.IN260
dateg[3] => Mux6.IN260
dateg[3] => Mux7.IN260
dateg[4] => Mux0.IN259
dateg[4] => Mux1.IN259
dateg[4] => Mux2.IN259
dateg[4] => Mux3.IN259
dateg[4] => Mux4.IN259
dateg[4] => Mux5.IN259
dateg[4] => Mux6.IN259
dateg[4] => Mux7.IN259
dateg[5] => Mux0.IN258
dateg[5] => Mux1.IN258
dateg[5] => Mux2.IN258
dateg[5] => Mux3.IN258
dateg[5] => Mux4.IN258
dateg[5] => Mux5.IN258
dateg[5] => Mux6.IN258
dateg[5] => Mux7.IN258
dateg[6] => Mux0.IN257
dateg[6] => Mux1.IN257
dateg[6] => Mux2.IN257
dateg[6] => Mux3.IN257
dateg[6] => Mux4.IN257
dateg[6] => Mux5.IN257
dateg[6] => Mux6.IN257
dateg[6] => Mux7.IN257
dateg[7] => Mux0.IN256
dateg[7] => Mux1.IN256
dateg[7] => Mux2.IN256
dateg[7] => Mux3.IN256
dateg[7] => Mux4.IN256
dateg[7] => Mux5.IN256
dateg[7] => Mux6.IN256
dateg[7] => Mux7.IN256
dater[0] => Mux8.IN263
dater[0] => Mux9.IN263
dater[0] => Mux10.IN263
dater[0] => Mux11.IN263
dater[0] => Mux12.IN263
dater[0] => Mux13.IN263
dater[0] => Mux14.IN263
dater[0] => Mux15.IN263
dater[1] => Mux8.IN262
dater[1] => Mux9.IN262
dater[1] => Mux10.IN262
dater[1] => Mux11.IN262
dater[1] => Mux12.IN262
dater[1] => Mux13.IN262
dater[1] => Mux14.IN262
dater[1] => Mux15.IN262
dater[2] => Mux8.IN261
dater[2] => Mux9.IN261
dater[2] => Mux10.IN261
dater[2] => Mux11.IN261
dater[2] => Mux12.IN261
dater[2] => Mux13.IN261
dater[2] => Mux14.IN261
dater[2] => Mux15.IN261
dater[3] => Mux8.IN260
dater[3] => Mux9.IN260
dater[3] => Mux10.IN260
dater[3] => Mux11.IN260
dater[3] => Mux12.IN260
dater[3] => Mux13.IN260
dater[3] => Mux14.IN260
dater[3] => Mux15.IN260
dater[4] => Mux8.IN259
dater[4] => Mux9.IN259
dater[4] => Mux10.IN259
dater[4] => Mux11.IN259
dater[4] => Mux12.IN259
dater[4] => Mux13.IN259
dater[4] => Mux14.IN259
dater[4] => Mux15.IN259
dater[5] => Mux8.IN258
dater[5] => Mux9.IN258
dater[5] => Mux10.IN258
dater[5] => Mux11.IN258
dater[5] => Mux12.IN258
dater[5] => Mux13.IN258
dater[5] => Mux14.IN258
dater[5] => Mux15.IN258
dater[6] => Mux8.IN257
dater[6] => Mux9.IN257
dater[6] => Mux10.IN257
dater[6] => Mux11.IN257
dater[6] => Mux12.IN257
dater[6] => Mux13.IN257
dater[6] => Mux14.IN257
dater[6] => Mux15.IN257
dater[7] => Mux8.IN256
dater[7] => Mux9.IN256
dater[7] => Mux10.IN256
dater[7] => Mux11.IN256
dater[7] => Mux12.IN256
dater[7] => Mux13.IN256
dater[7] => Mux14.IN256
dater[7] => Mux15.IN256
dgin[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
dgin[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
dgin[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
dgin[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
dgin[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
dgin[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
dgin[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
dgin[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
drin[0] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
drin[1] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
drin[2] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
drin[3] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
drin[4] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
drin[5] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
drin[6] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
drin[7] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE


|led_control|rom_green:inst2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
address[12] => altsyncram:altsyncram_component.address_a[12]
address[13] => altsyncram:altsyncram_component.address_a[13]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|led_control|rom_green:inst2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_d671:auto_generated.address_a[0]
address_a[1] => altsyncram_d671:auto_generated.address_a[1]
address_a[2] => altsyncram_d671:auto_generated.address_a[2]
address_a[3] => altsyncram_d671:auto_generated.address_a[3]
address_a[4] => altsyncram_d671:auto_generated.address_a[4]
address_a[5] => altsyncram_d671:auto_generated.address_a[5]
address_a[6] => altsyncram_d671:auto_generated.address_a[6]
address_a[7] => altsyncram_d671:auto_generated.address_a[7]
address_a[8] => altsyncram_d671:auto_generated.address_a[8]
address_a[9] => altsyncram_d671:auto_generated.address_a[9]
address_a[10] => altsyncram_d671:auto_generated.address_a[10]
address_a[11] => altsyncram_d671:auto_generated.address_a[11]
address_a[12] => altsyncram_d671:auto_generated.address_a[12]
address_a[13] => altsyncram_d671:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_d671:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_d671:auto_generated.q_a[0]
q_a[1] <= altsyncram_d671:auto_generated.q_a[1]
q_a[2] <= altsyncram_d671:auto_generated.q_a[2]
q_a[3] <= altsyncram_d671:auto_generated.q_a[3]
q_a[4] <= altsyncram_d671:auto_generated.q_a[4]
q_a[5] <= altsyncram_d671:auto_generated.q_a[5]
q_a[6] <= altsyncram_d671:auto_generated.q_a[6]
q_a[7] <= altsyncram_d671:auto_generated.q_a[7]
q_b[0] <= <GND>


|led_control|rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1