led_scan.hif

用DE2板子实现的控制64乘64点阵LED的点亮,硬件需要de2板及led点阵

address_a3
-1
3
address_a2
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
green.mif
bdfc83f099728be1f395b3cec3f2f4ea
}
# end
# entity
LED_SCAN
# storage
db|led_scan.(0).cnf
db|led_scan.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
led_scan.vhd
49fe314a6493612c730163ec96645e
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
LED_SCAN:inst
}
# end
# entity
led_control
# storage
db|led_scan.(2).cnf
db|led_scan.(2).cnf
# case_insensitive
# source_file
led_control.bdf
ab24783a52ac491d9e2d8c5a18a2cc19
24
# hierarchies {
|
}
# end
# entity
rom_green
# storage
db|led_scan.(3).cnf
db|led_scan.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom_green.vhd
4f18653c4f6c1d1ed852bade9afad
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rom_green:inst2
}
# end
# entity
altsyncram
# storage
db|led_scan.(8).cnf
db|led_scan.(8).cnf
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
14
PARAMETER_DEC
USR
NUMWORDS_A
16384
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
green0.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_d671
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
c:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
c:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
c:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
rom_green:inst2|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_d671
# storage
db|led_scan.(11).cnf
db|led_scan.(11).cnf
# case_insensitive
# source_file
db|altsyncram_d671.tdf
af9f455222753bdfc0b7b3dc3692b092
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
green0.mif
ddcaf5775065758e23f82cd056b5683b
}
# hierarchies {
rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated
}
# end
# entity
decode_4oa
# storage
db|led_scan.(12).cnf
db|led_scan.(12).cnf
# case_insensitive
# source_file
db|decode_4oa.tdf
b17b39213e502bf4d783d4e1d186921
6
# used_port {
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
data1
-1
3
data0
-1
3
enable
-1
2
}
# hierarchies {
rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|decode_4oa:deep_decode
rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated|decode_4oa:deep_decode
}
# end
# entity
mux_kib
# storage
db|led_scan.(13).cnf
db|led_scan.(13).cnf
# case_insensitive
# source_file
db|mux_kib.tdf
3bb22a7d52dd86d33e60789b8e17b44f
6
# used_port {
sel1
-1
3
sel0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2
rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated|mux_kib:mux2
}
# end
# entity
rom_red
# storage
db|led_scan.(14).cnf
db|led_scan.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom_red.vhd
a570f5125032ee1bace6080270188d
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rom_red:inst1
}
# end
# entity
altsyncram
# storage
db|led_scan.(15).cnf
db|led_scan.(15).cnf
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
14
PARAMETER_DEC
USR
NUMWORDS_A
16384
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
red0.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_nv61
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
c:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
c:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
c:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
rom_red:inst1|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_nv61
# storage
db|led_scan.(16).cnf
db|led_scan.(16).cnf
# case_insensitive
# source_file
db|altsyncram_nv61.tdf
13c9f9fe4fcfcfdc78e96d7cfebb1361
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
red0.mif
c8a8f02f90aa3abc65f958080531f8
}
# hierarchies {
rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated
}
# end
# complete