📄 led_scan.map.rpt
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; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; green0.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_d671 ; Untyped ;
+------------------------------------+-----------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom_red:inst1|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------+-------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Integer ;
; WIDTHAD_A ; 14 ; Integer ;
; NUMWORDS_A ; 16384 ; Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; red0.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_nv61 ; Untyped ;
+------------------------------------+-----------------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Jan 11 15:34:07 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led_scan -c led_scan
Info: Found 2 design units, including 1 entities, in source file led_scan.vhd
Info: Found design unit 1: LED_SCAN-LIN
Info: Found entity 1: LED_SCAN
Info: Found 2 design units, including 1 entities, in source file CUS_r_CORRECTION .vhd
Info: Found design unit 1: CUS_r_CORRECTION-LIN
Info: Found entity 1: CUS_r_CORRECTION
Info: Found 1 design units, including 1 entities, in source file led_control.bdf
Info: Found entity 1: led_control
Info: Elaborating entity "led_control" for the top level hierarchy
Info: Elaborating entity "LED_SCAN" for hierarchy "LED_SCAN:inst"
Info: Elaborating entity "CUS_r_CORRECTION" for hierarchy "CUS_r_CORRECTION:inst3"
Warning: Using design file rom_green.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: rom_green-SYN
Info: Found entity 1: rom_green
Info: Elaborating entity "rom_green" for hierarchy "rom_green:inst2"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "rom_green:inst2|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "rom_green:inst2|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_d671.tdf
Info: Found entity 1: altsyncram_d671
Info: Elaborating entity "altsyncram_d671" for hierarchy "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/decode_4oa.tdf
Info: Found entity 1: decode_4oa
Info: Elaborating entity "decode_4oa" for hierarchy "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|decode_4oa:deep_decode"
Info: Found 1 design units, including 1 entities, in source file db/mux_kib.tdf
Info: Found entity 1: mux_kib
Info: Elaborating entity "mux_kib" for hierarchy "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|mux_kib:mux2"
Warning: Using design file rom_red.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: rom_red-SYN
Info: Found entity 1: rom_red
Info: Elaborating entity "rom_red" for hierarchy "rom_red:inst1"
Info: Elaborating entity "altsyncram" for hierarchy "rom_red:inst1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "rom_red:inst1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_nv61.tdf
Info: Found entity 1: altsyncram_nv61
Info: Elaborating entity "altsyncram_nv61" for hierarchy "rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated"
Warning: Reduced register "LED_SCAN:inst|addcon[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|addcon[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|addcon[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|addcon[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|addcon[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|addcon[5]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|address_reg_a[1]" merged to single register "rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated|address_reg_a[1]"
Info: Duplicate register "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|address_reg_a[0]" merged to single register "rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated|address_reg_a[0]"
Info: Duplicate register "rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated|address_reg_a[3]" merged to single register "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|address_reg_a[3]"
Info: Duplicate register "rom_red:inst1|altsyncram:altsyncram_component|altsyncram_nv61:auto_generated|address_reg_a[2]" merged to single register "rom_green:inst2|altsyncram:altsyncram_component|altsyncram_d671:auto_generated|address_reg_a[2]"
Warning: Reduced register "LED_SCAN:inst|DIV_COUNT[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|DIV_COUNT[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|DIV_COUNT[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "LED_SCAN:inst|DIV_COUNT[1]" with stuck data_in port to stuck value GND
Info: Implemented 494 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 9 output pins
Info: Implemented 420 logic cells
Info: Implemented 64 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Processing ended: Fri Jan 11 15:34:31 2008
Info: Elapsed time: 00:00:25
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