📄 pll1_waveforms.html

📁 用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

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<html>
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<title>Sample Waveforms for pll1.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file pll1.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll1.vhd. The design pll1.vhd has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 100000 ps. CLK0 multiply by = 2, CLK0 divide by = 0, CLK0 phase_shift = 0 </P>

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