cnt10.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity cnt10 is
port(clk100M:in std_logic;
     clk10M:out std_logic);
end cnt10;

architecture rtl of cnt10 is
signal data:integer range 0 to 9;
begin

process(clk100M)
begin
    if(clk100M'event and clk100M='1')then
        if(data=9)then
           data<=0;
     	   clk10M<='1';
        else 
           data<=data+1;
           clk10M<='0';
        end if;
   end if;

end process;
end rtl;