am_adj.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 56 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity am_adj is
port(clk10k,key:in std_logic; 
 	 dataout:out std_logic_vector(7 downto 0);
     am_adj_coefi:out std_logic_vector(3 downto 0));
end am_adj;

architecture rtl of am_adj is
signal data:integer range 0 to 255;
signal datb:integer range 0 to 10;
signal cont_en:std_logic;
begin

process(clk10k)
begin
    if(clk10k'event and clk10k='1')then
       if(cont_en='1')then 
         if(data>=199)then
            data<=199;
          else 
            data<=data+1;
          end if;
  		end if;
   end if;
dataout<=conv_std_logic_vector(data,8);
end process;


process(clk10k,key)
begin
    if(clk10k'event and clk10k='1')then
   		if(key='1')then
          cont_en<='1';
        elsif(data=199)then
    	 cont_en<='0';
  	    end if;
	end if;	
end process;

process(cont_en)
begin
    if(cont_en'event and cont_en='1')then
         if(datb=10)then
            datb<=0;
          else 
            datb<=datb+1;
          end if;
   end if;
am_adj_coefi<=conv_std_logic_vector(datb,4);
end process;

end rtl;