psk_m.vhd

来自「用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity psk_m is
port(q:in std_logic;
     psk_in:in std_logic_vector(7 downto 0);
     psk_out:out std_logic_vector(7 downto 0));
end psk_m;

architecture behav of psk_m is
begin

process(q)
begin
           if(q='1')then
          psk_out<=psk_in;
        else
 		  psk_out<=not psk_in;
		end if;
   
end process;

end behav;