sin_gen.tan.qmsg

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~UPDATEUSER " "Info: Assuming node \"altera_internal_jtag~UPDATEUSER\" is an undefined clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~UPDATEUSER" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~CLKDRUSER " "Info: Assuming node \"altera_internal_jtag~CLKDRUSER\" is an undefined clock" {  } { { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~CLKDRUSER" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "15 " "Warning: Found 15 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "am_modulate:inst18\|am_adjust:inst10\|key1 " "Info: Detected ripple clock \"am_modulate:inst18\|am_adjust:inst10\|key1\" as buffer" {  } { { "am_adjust.vhd" "" { Text "F:/debug/am/am_adjust.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "am_modulate:inst18\|am_adjust:inst10\|key1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "am_modulate:inst18\|am_adjust:inst10\|key0 " "Info: Detected ripple clock \"am_modulate:inst18\|am_adjust:inst10\|key0\" as buffer" {  } { { "am_adjust.vhd" "" { Text "F:/debug/am/am_adjust.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "am_modulate:inst18\|am_adjust:inst10\|key0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "am_modulate:inst18\|am_adjust:inst10\|key_en~21 " "Info: Detected gated clock \"am_modulate:inst18\|am_adjust:inst10\|key_en~21\" as buffer" {  } { { "am_adjust.vhd" "" { Text "F:/debug/am/am_adjust.vhd" 13 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "am_modulate:inst18\|am_adjust:inst10\|key_en~21" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "multi_clk:inst2\|cnt10:inst2\|clk10M " "Info: Detected ripple clock \"multi_clk:inst2\|cnt10:inst2\|clk10M\" as buffer" {  } { { "cnt10.vhd" "" { Text "F:/debug/am/cnt10.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "multi_clk:inst2\|cnt10:inst2\|clk10M" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "multi_clk:inst2\|cnt10:inst3\|clk10M " "Info: Detected ripple clock \"multi_clk:inst2\|cnt10:inst3\|clk10M\" as buffer" {  } { { "cnt10.vhd" "" { Text "F:/debug/am/cnt10.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "multi_clk:inst2\|cnt10:inst3\|clk10M" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "multi_clk:inst2\|cnt10:inst5\|clk10M " "Info: Detected ripple clock \"multi_clk:inst2\|cnt10:inst5\|clk10M\" as buffer" {  } { { "cnt10.vhd" "" { Text "F:/debug/am/cnt10.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "multi_clk:inst2\|cnt10:inst5\|clk10M" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "multi_clk:inst2\|cnt10:inst\|clk10M " "Info: Detected ripple clock \"multi_clk:inst2\|cnt10:inst\|clk10M\" as buffer" {  } { { "cnt10.vhd" "" { Text "F:/debug/am/cnt10.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "multi_clk:inst2\|cnt10:inst\|clk10M" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_word_gen:inst13\|key_delay:inst13\|key1 " "Info: Detected ripple clock \"fre_word_gen:inst13\|key_delay:inst13\|key1\" as buffer" {  } { { "key_delay.vhd" "" { Text "F:/debug/am/key_delay.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_word_gen:inst13\|key_delay:inst13\|key1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_word_gen:inst13\|key_delay:inst13\|key0 " "Info: Detected ripple clock \"fre_word_gen:inst13\|key_delay:inst13\|key0\" as buffer" {  } { { "key_delay.vhd" "" { Text "F:/debug/am/key_delay.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_word_gen:inst13\|key_delay:inst13\|key0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "multi_clk:inst2\|div40:inst4\|keyclk " "Info: Detected ripple clock \"multi_clk:inst2\|div40:inst4\|keyclk\" as buffer" {  } { { "div40.vhd" "" { Text "F:/debug/am/div40.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "multi_clk:inst2\|div40:inst4\|keyclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_word_gen:inst13\|key_delay:inst13\|key_1 " "Info: Detected ripple clock \"fre_word_gen:inst13\|key_delay:inst13\|key_1\" as buffer" {  } { { "key_delay.vhd" "" { Text "F:/debug/am/key_delay.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_word_gen:inst13\|key_delay:inst13\|key_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre_word_gen:inst13\|key_delay:inst13\|key_0 " "Info: Detected ripple clock \"fre_word_gen:inst13\|key_delay:inst13\|key_0\" as buffer" {  } { { "key_delay.vhd" "" { Text "F:/debug/am/key_delay.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_word_gen:inst13\|key_delay:inst13\|key_0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "fre_word_gen:inst13\|key_delay:inst13\|key_en100~22 " "Info: Detected gated clock \"fre_word_gen:inst13\|key_delay:inst13\|key_en100~22\" as buffer" {  } { { "key_delay.vhd" "" { Text "F:/debug/am/key_delay.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_word_gen:inst13\|key_delay:inst13\|key_en100~22" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "fre_word_gen:inst13\|key_delay:inst13\|key_en100k~22 " "Info: Detected gated clock \"fre_word_gen:inst13\|key_delay:inst13\|key_en100k~22\" as buffer" {  } { { "key_delay.vhd" "" { Text "F:/debug/am/key_delay.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fre_word_gen:inst13\|key_delay:inst13\|key_en100k~22" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "multi_clk:inst2\|cnt10:inst1\|clk10M " "Info: Detected ripple clock \"multi_clk:inst2\|cnt10:inst1\|clk10M\" as buffer" {  } { { "cnt10.vhd" "" { Text "F:/debug/am/cnt10.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "multi_clk:inst2\|cnt10:inst1\|clk10M" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}