shift_taps_aaq.tdf

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" NUMBER_OF_TAPS=1 TAP_DISTANCE=3 WIDTH=14 clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="DEDICATED_MULTIPLIER_CIRCUITRY=YES"
--VERSION_BEGIN 6.0 cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altshift_taps 2006:01:26:13:08:24:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION altsyncram_r831 (address_a[1..0], address_b[1..0], clock0, clock1, clocken0, clocken1, data_a[13..0], wren_a)
RETURNS ( q_b[13..0]);
FUNCTION add_sub_und (dataa[1..0], datab[1..0])
RETURNS ( result[1..0]);
FUNCTION cntr_0fc (clk_en, clock)
RETURNS ( q[1..0]);

--synthesis_resources = lut 6 M4K 14 
SUBDESIGN shift_taps_aaq
( 
	clock	:	input;
	shiftin[13..0]	:	input;
	shiftout[13..0]	:	output;
	taps[13..0]	:	output;
) 
VARIABLE 
	altsyncram4 : altsyncram_r831;
	dffe3a[1..0] : dffe;
	add_sub2 : add_sub_und;
	cntr1 : cntr_0fc;
	clken	: NODE;
	rdaddress[1..0]	: WIRE;

BEGIN 
	altsyncram4.address_a[] = cntr1.q[];
	altsyncram4.address_b[] = rdaddress[];
	altsyncram4.clock0 = clock;
	altsyncram4.clock1 = clock;
	altsyncram4.clocken0 = clken;
	altsyncram4.clocken1 = clken;
	altsyncram4.data_a[] = ( shiftin[]);
	altsyncram4.wren_a = B"1";
	dffe3a[].CLK = clock;
	dffe3a[].D = ( (! add_sub2.result[1..1]), add_sub2.result[0..0]);
	dffe3a[].ENA = clken;
	add_sub2.dataa[] = cntr1.q[];
	add_sub2.datab[] = B"00";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	clken = VCC;
	rdaddress[] = ( (! dffe3a[1..1].Q), dffe3a[0..0].Q);
	shiftout[13..0] = altsyncram4.q_b[13..0];
	taps[] = altsyncram4.q_b[];
END;
--VALID FILE