sin_gen.hier_info

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_cen:ux0123
clk => clk~0.IN1
clken => clken~0.IN1
raxx[0] => raxx_w[0].IN1
raxx[1] => raxx_w[1].IN1
raxx[2] => raxx_w[2].IN1
raxx[3] => raxx_w[3].IN1
raxx[4] => raxx_w[4].IN1
raxx[5] => raxx_w[5].IN1
raxx[6] => raxx_w[6].IN1
raxx[7] => raxx_w[7].IN1
srw_int_res[0] <= altsyncram:altsyncram_component0.q_a
srw_int_res[1] <= altsyncram:altsyncram_component0.q_a
srw_int_res[2] <= altsyncram:altsyncram_component0.q_a
srw_int_res[3] <= altsyncram:altsyncram_component0.q_a
srw_int_res[4] <= altsyncram:altsyncram_component0.q_a
srw_int_res[5] <= altsyncram:altsyncram_component0.q_a
srw_int_res[6] <= altsyncram:altsyncram_component0.q_a
srw_int_res[7] <= altsyncram:altsyncram_component0.q_a


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_d791:auto_generated.address_a[0]
address_a[1] => altsyncram_d791:auto_generated.address_a[1]
address_a[2] => altsyncram_d791:auto_generated.address_a[2]
address_a[3] => altsyncram_d791:auto_generated.address_a[3]
address_a[4] => altsyncram_d791:auto_generated.address_a[4]
address_a[5] => altsyncram_d791:auto_generated.address_a[5]
address_a[6] => altsyncram_d791:auto_generated.address_a[6]
address_a[7] => altsyncram_d791:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_d791:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_d791:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_d791:auto_generated.q_a[0]
q_a[1] <= altsyncram_d791:auto_generated.q_a[1]
q_a[2] <= altsyncram_d791:auto_generated.q_a[2]
q_a[3] <= altsyncram_d791:auto_generated.q_a[3]
q_a[4] <= altsyncram_d791:auto_generated.q_a[4]
q_a[5] <= altsyncram_d791:auto_generated.q_a[5]
q_a[6] <= altsyncram_d791:auto_generated.q_a[6]
q_a[7] <= altsyncram_d791:auto_generated.q_a[7]
q_b[0] <= <GND>


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_cen:ux0123|altsyncram:altsyncram_component0|altsyncram_d791:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|mac_i_lpmd:m0
clk => clk~0.IN3
reset => result_a~34.OUTPUTSELECT
reset => result_a~35.OUTPUTSELECT
reset => result_a~36.OUTPUTSELECT
reset => result_a~37.OUTPUTSELECT
reset => result_a~38.OUTPUTSELECT
reset => result_a~39.OUTPUTSELECT
reset => result_a~40.OUTPUTSELECT
reset => result_a~41.OUTPUTSELECT
reset => result_a~42.OUTPUTSELECT
reset => result_a~43.OUTPUTSELECT
reset => result_a~44.OUTPUTSELECT
reset => result_a~45.OUTPUTSELECT
reset => result_a~46.OUTPUTSELECT
reset => result_a~47.OUTPUTSELECT
reset => result_a~48.OUTPUTSELECT
reset => result_a~49.OUTPUTSELECT
reset => result_a~50.OUTPUTSELECT
reset => result_b~34.OUTPUTSELECT
reset => result_b~35.OUTPUTSELECT
reset => result_b~36.OUTPUTSELECT
reset => result_b~37.OUTPUTSELECT
reset => result_b~38.OUTPUTSELECT
reset => result_b~39.OUTPUTSELECT
reset => result_b~40.OUTPUTSELECT
reset => result_b~41.OUTPUTSELECT
reset => result_b~42.OUTPUTSELECT
reset => result_b~43.OUTPUTSELECT
reset => result_b~44.OUTPUTSELECT
reset => result_b~45.OUTPUTSELECT
reset => result_b~46.OUTPUTSELECT
reset => result_b~47.OUTPUTSELECT
reset => result_b~48.OUTPUTSELECT
reset => result_b~49.OUTPUTSELECT
reset => result_b~50.OUTPUTSELECT
clken => clken~0.IN3
a_or_s => a_or_s~0.IN1
dataa_0[0] => dataa_0[0]~7.IN1
dataa_0[1] => dataa_0[1]~6.IN1
dataa_0[2] => dataa_0[2]~5.IN1
dataa_0[3] => dataa_0[3]~4.IN1
dataa_0[4] => dataa_0[4]~3.IN1
dataa_0[5] => dataa_0[5]~2.IN1
dataa_0[6] => dataa_0[6]~1.IN1
dataa_0[7] => dataa_0[7]~0.IN1
dataa_1[0] => dataa_1[0]~7.IN1
dataa_1[1] => dataa_1[1]~6.IN1
dataa_1[2] => dataa_1[2]~5.IN1
dataa_1[3] => dataa_1[3]~4.IN1
dataa_1[4] => dataa_1[4]~3.IN1
dataa_1[5] => dataa_1[5]~2.IN1
dataa_1[6] => dataa_1[6]~1.IN1
dataa_1[7] => dataa_1[7]~0.IN1
datab_0[0] => datab_0[0]~7.IN1
datab_0[1] => datab_0[1]~6.IN1
datab_0[2] => datab_0[2]~5.IN1
datab_0[3] => datab_0[3]~4.IN1
datab_0[4] => datab_0[4]~3.IN1
datab_0[5] => datab_0[5]~2.IN1
datab_0[6] => datab_0[6]~1.IN1
datab_0[7] => datab_0[7]~0.IN1
datab_1[0] => datab_1[0]~7.IN1
datab_1[1] => datab_1[1]~6.IN1
datab_1[2] => datab_1[2]~5.IN1
datab_1[3] => datab_1[3]~4.IN1
datab_1[4] => datab_1[4]~3.IN1
datab_1[5] => datab_1[5]~2.IN1
datab_1[6] => datab_1[6]~1.IN1
datab_1[7] => datab_1[7]~0.IN1
result[0] <= las:a_0.result
result[1] <= las:a_0.result
result[2] <= las:a_0.result
result[3] <= las:a_0.result
result[4] <= las:a_0.result
result[5] <= las:a_0.result
result[6] <= las:a_0.result
result[7] <= las:a_0.result
result[8] <= las:a_0.result
result[9] <= las:a_0.result
result[10] <= las:a_0.result
result[11] <= las:a_0.result
result[12] <= las:a_0.result
result[13] <= las:a_0.result
result[14] <= las:a_0.result
result[15] <= las:a_0.result
result[16] <= las:a_0.result


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|mac_i_lpmd:m0|lmsd:m_0
clk => clk~0.IN1
dataa[0] => dataa[0]~7.IN1
dataa[1] => dataa[1]~6.IN1
dataa[2] => dataa[2]~5.IN1
dataa[3] => dataa[3]~4.IN1
dataa[4] => dataa[4]~3.IN1
dataa[5] => dataa[5]~2.IN1
dataa[6] => dataa[6]~1.IN1
dataa[7] => dataa[7]~0.IN1
datab[0] => datab[0]~7.IN1
datab[1] => datab[1]~6.IN1
datab[2] => datab[2]~5.IN1
datab[3] => datab[3]~4.IN1
datab[4] => datab[4]~3.IN1
datab[5] => datab[5]~2.IN1
datab[6] => datab[6]~1.IN1
datab[7] => datab[7]~0.IN1
clken => clken~0.IN1
result[0] <= lpm_mult:lpm_mult_component.result
result[1] <= lpm_mult:lpm_mult_component.result
result[2] <= lpm_mult:lpm_mult_component.result
result[3] <= lpm_mult:lpm_mult_component.result
result[4] <= lpm_mult:lpm_mult_co