sin_gen.hier_info

用DE2板子实现的正选信号发生器,需安装quartus2软件,硬件需要DE2的开发板

q_b[7] <= altsyncram:altsyncram_component.q_b


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_ee72:auto_generated.data_a[0]
data_a[1] => altsyncram_ee72:auto_generated.data_a[1]
data_a[2] => altsyncram_ee72:auto_generated.data_a[2]
data_a[3] => altsyncram_ee72:auto_generated.data_a[3]
data_a[4] => altsyncram_ee72:auto_generated.data_a[4]
data_a[5] => altsyncram_ee72:auto_generated.data_a[5]
data_a[6] => altsyncram_ee72:auto_generated.data_a[6]
data_a[7] => altsyncram_ee72:auto_generated.data_a[7]
data_b[0] => altsyncram_ee72:auto_generated.data_b[0]
data_b[1] => altsyncram_ee72:auto_generated.data_b[1]
data_b[2] => altsyncram_ee72:auto_generated.data_b[2]
data_b[3] => altsyncram_ee72:auto_generated.data_b[3]
data_b[4] => altsyncram_ee72:auto_generated.data_b[4]
data_b[5] => altsyncram_ee72:auto_generated.data_b[5]
data_b[6] => altsyncram_ee72:auto_generated.data_b[6]
data_b[7] => altsyncram_ee72:auto_generated.data_b[7]
address_a[0] => altsyncram_ee72:auto_generated.address_a[0]
address_a[1] => altsyncram_ee72:auto_generated.address_a[1]
address_a[2] => altsyncram_ee72:auto_generated.address_a[2]
address_a[3] => altsyncram_ee72:auto_generated.address_a[3]
address_a[4] => altsyncram_ee72:auto_generated.address_a[4]
address_a[5] => altsyncram_ee72:auto_generated.address_a[5]
address_a[6] => altsyncram_ee72:auto_generated.address_a[6]
address_a[7] => altsyncram_ee72:auto_generated.address_a[7]
address_b[0] => altsyncram_ee72:auto_generated.address_b[0]
address_b[1] => altsyncram_ee72:auto_generated.address_b[1]
address_b[2] => altsyncram_ee72:auto_generated.address_b[2]
address_b[3] => altsyncram_ee72:auto_generated.address_b[3]
address_b[4] => altsyncram_ee72:auto_generated.address_b[4]
address_b[5] => altsyncram_ee72:auto_generated.address_b[5]
address_b[6] => altsyncram_ee72:auto_generated.address_b[6]
address_b[7] => altsyncram_ee72:auto_generated.address_b[7]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ee72:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_ee72:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ee72:auto_generated.q_a[0]
q_a[1] <= altsyncram_ee72:auto_generated.q_a[1]
q_a[2] <= altsyncram_ee72:auto_generated.q_a[2]
q_a[3] <= altsyncram_ee72:auto_generated.q_a[3]
q_a[4] <= altsyncram_ee72:auto_generated.q_a[4]
q_a[5] <= altsyncram_ee72:auto_generated.q_a[5]
q_a[6] <= altsyncram_ee72:auto_generated.q_a[6]
q_a[7] <= altsyncram_ee72:auto_generated.q_a[7]
q_b[0] <= altsyncram_ee72:auto_generated.q_b[0]
q_b[1] <= altsyncram_ee72:auto_generated.q_b[1]
q_b[2] <= altsyncram_ee72:auto_generated.q_b[2]
q_b[3] <= altsyncram_ee72:auto_generated.q_b[3]
q_b[4] <= altsyncram_ee72:auto_generated.q_b[4]
q_b[5] <= altsyncram_ee72:auto_generated.q_b[5]
q_b[6] <= altsyncram_ee72:auto_generated.q_b[6]
q_b[7] <= altsyncram_ee72:auto_generated.q_b[7]


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_dp_cen:ux0220|altsyncram:altsyncram_component|altsyncram_ee72:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_b[0] => ram_block1a0.PORTBDATAIN
data_b[1] => ram_block1a1.PORTBDATAIN
data_b[2] => ram_block1a2.PORTBDATAIN
data_b[3] => ram_block1a3.PORTBDATAIN
data_b[4] => ram_block1a4.PORTBDATAIN
data_b[5] => ram_block1a5.PORTBDATAIN
data_b[6] => ram_block1a6.PORTBDATAIN
data_b[7] => ram_block1a7.PORTBDATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_cen:ux0122
clk => clk~0.IN1
clken => clken~0.IN1
raxx[0] => raxx_w[0].IN1
raxx[1] => raxx_w[1].IN1
raxx[2] => raxx_w[2].IN1
raxx[3] => raxx_w[3].IN1
raxx[4] => raxx_w[4].IN1
raxx[5] => raxx_w[5].IN1
raxx[6] => raxx_w[6].IN1
raxx[7] => raxx_w[7].IN1
srw_int_res[0] <= altsyncram:altsyncram_component0.q_a
srw_int_res[1] <= altsyncram:altsyncram_component0.q_a
srw_int_res[2] <= altsyncram:altsyncram_component0.q_a
srw_int_res[3] <= altsyncram:altsyncram_component0.q_a
srw_int_res[4] <= altsyncram:altsyncram_component0.q_a
srw_int_res[5] <= altsyncram:altsyncram_component0.q_a
srw_int_res[6] <= altsyncram:altsyncram_component0.q_a
srw_int_res[7] <= altsyncram:altsyncram_component0.q_a


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_i791:auto_generated.address_a[0]
address_a[1] => altsyncram_i791:auto_generated.address_a[1]
address_a[2] => altsyncram_i791:auto_generated.address_a[2]
address_a[3] => altsyncram_i791:auto_generated.address_a[3]
address_a[4] => altsyncram_i791:auto_generated.address_a[4]
address_a[5] => altsyncram_i791:auto_generated.address_a[5]
address_a[6] => altsyncram_i791:auto_generated.address_a[6]
address_a[7] => altsyncram_i791:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_i791:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_i791:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_i791:auto_generated.q_a[0]
q_a[1] <= altsyncram_i791:auto_generated.q_a[1]
q_a[2] <= altsyncram_i791:auto_generated.q_a[2]
q_a[3] <= altsyncram_i791:auto_generated.q_a[3]
q_a[4] <= altsyncram_i791:auto_generated.q_a[4]
q_a[5] <= altsyncram_i791:auto_generated.q_a[5]
q_a[6] <= altsyncram_i791:auto_generated.q_a[6]
q_a[7] <= altsyncram_i791:auto_generated.q_a[7]
q_b[0] <= <GND>


|sin_gen|NCO_DDS:inst|NCO_DDS_st:NCO_DDS_st_inst|asj_nco_as_m_cen:ux0122|altsyncram:altsyncram_component0|altsyncram_i791:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2